Writing a 1 to this bit resets the PHY PCS registers. When the reset operation is done, this bit is cleared to 0 automatically. PHY Vendor Specific registers (with MMD = 1F) will not be cleared.
Straps are not re-latched with this reset. Straps are re-latched only during power up and pin reset.

When MII loopback mode is activated, the transmitted data presented on MII TXD is looped back to MII RXD internally.

When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000), writing to this bit allows the port speed to be selected.

If Auto-Negotiation is disabled, bit[8] and bit[13] of this register determine the port speed and duplex mode.

The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. To control the power down mechanism, this bit is OR'ed with the input from the INT/PWDN_N pin. When the active low INT/PWDN_N is asserted, this bit is set.
Programmed register are not reset to default in power down. Since all state machines undergo reset so status bits (RO) may show a change in value.

If Auto-Negotiation is disabled (bit[12] = 0), bit[9] is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.

When Auto-Negotiation is disabled, writing to this bit allows the port Duplex capability to be selected.

When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion to TX_EN.

If this bit is set to 1, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround.

Far End Fault indication or notification from Link Partner of Remote Fault. This bit is cleared on read or reset.

This bit only has meaning for 10Base-Te operation.

Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.

Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.

Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

In normal RMII mode, if the line is not idle, CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to "2" (0010). This situation remains for the duration of the receive event. While in enhanced mode, CRS_DV is disqualified and de-asserted when the False Carrier is detected. This status also remains for the duration of the receive event. In addition, in normal mode, the start of the packet is intact. Each symbol error is indicatied by setting RX_ER high. The data on RXD is replaced with "1" starting with the first symbol error. While in enhanced mode, the CRS_DV is de-asserted with the first symbol error.

This mode allows recovery from short interference and continue to hold the link up for a few additional mSec until the short interference is gone and the signal is OK. Under Normal Link Loss operation, Link status will go down approximately 250μs from signal loss.

If both link partners are configured to work in Force 100Base-TX mode (Auto-Negotiation disabled), this mode enables Automatic MDI/MDIX resolution in a shortened time.

If link partners are configured for operational modes that are not supported by normal Auto-MDIX, Robust Auto-MDIX allows MDI/MDIX resolution and prevents deadlock.

When the DP83822 is strapped for 100 Mbps operation with Auto-MDIX capabilities, Robust Auto-MDIX will be automatically set to aid in MDI/MDIX resolution and deadlock prevention.

The PHY Auto-Negotiaties using timer setting according to Fast Auto-Negotiation Select bits (bits[3:2] in this register).

When Fast RX_DV is enabled, RX_DV will assert high on receive packet due to detection of the /J/ symbol only. If a consecutive /K/ does not appear, RX_ER is generated. In normal mode, RX_DV will only be asserted after detection of /JK/.

In Fast Auto MDIX and in Robust Auto-MDIX modes (bit[6] and bit[5] in register CR1), this bit is automatically set.

In Extended Full-Duplex ability, when the PHY is set to Auto-Negotiation or Force 100Base-TX and the link partner is operated in Force 100Base-TX, the link is always Full-Duplex. When disabled, the decision to work in Full-Duplex or Half-Duplex mode follows IEEE specification.

In Enhanced LED Link mode, TX/RX BLINK on activity is disabled for this LED pin. LED will only indicate LINK for established 100Base-TX Full-Duplex links.

In Isolate MII, MII outputs are isolated when Half-Duplex link established for 100Base-TX or when Half-Duplex or Full-Duplex link established for 10Base-Te.

Detection of odd-nibble will extend TX_EN by one additional TX_CLK cycle and behaves as if TX_ER were asserted during that additional cycle

This option can be enabled in parallel to the other fast link down modes in bits[3:0].

Port Mirror Function:
To enable port mirroring, set this bit and bit [5] high.

Port Mirror Function:
To enable port mirroring, set this bit and bit[6] high.

Bit 3 Drop the link based on RX Error count of the MII interface. When a predefined number of 32 RX Error occurences in a 10μs interval is reached, the link will be dropped.

Bit 2 Drop the link based on MLT3 Error count (Violation of the MLT3 coding in the DSP output). When a predefined number of 20 MLT3 Error occurences in a 10μs interval is reached, the link will be dropped.

Bit 1 Drop the link based on Low SNR Threshold. When a predefined number of 20 Threshold crossing occurences in a 10μs interval is reached, the link will be dropped.

Bit 0 Drop the link based on Signal/Energy Loss indication. When the Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10μs.

The Fast Link Down function is an OR of all 5 options (bit[10] and bits[3:0]), the designer can enable any combination of these conditions.

Status Registers that latch high each time a given Fast Link Down mode is activated and causes a link drop (assuming the modes were enabled)

Receive error event has occured since last read of RECR register (address 0x0015). This bit will be cleared upon a read of the RECR register.

This bit is a duplication of bit[4] in the 10BTSCR register (address 0x001A). This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register.

False Carrier event has occurred since last read of FCSCR register (address 0x0014). This bit will be cleared upon a read of the FCSR register.

Note: During EEE_LPI the value of this register bit should be ignored

Note: During EEE_LPI the value of this register bit should be ignored

This bit is a duplicate of Page Received (bit[1]) in the ANER register and it is cleared on read of the ANER register (address 0x0006).

Interrupt source can be determined by reading the MISR register (0x0012). Reading the MISR will clear this interrupt bit indication.

Fault criteria: notification from link partner of Remote Fault via Auto-Negotiation. Cleared on read of BMSR register (address 0x0001) or by reset.

This bit is a duplicate of the Jabber Detect bit in the BMSR register (address 0x0001) and will not be cleared upon a read of the PHYSTS register.

This bit is duplicated from the Link Status bit in the BMSR register (address 0x0001) and will not be cleared upon a read of the PHYSTS register.

Note: clock circuitry can be disabled only in IEEE power down mode.

Power Save Mode Enable (bit[14]) must be set to '1' for power save modes to be enabled.

This FIFO is used to adjust RX (receive) clock rate to TX clock rate. FIFO depth needs to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.

Note: When in Half-Duplex mode, Collision will always be active.

Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.

Enable interrupt dependent on the event enables in the MISR register (address 0x0012).

Enable active low interrupt events via the INT/PWDN_N pin by configuring the INT/PWDN_N pin as an output.

False Carrier counter (Register FCSCR, address 0x0014) exceeds half-full interrupt is pending.

Receiver Error counter (Register RECR, address 0x0015) exceeds half-full interrupt is pending.

Continuous mode, when the BIST Error counter reaches its max value, a pulse is generated and the counter starts counting from zero again. When in Single mode, if the BIST Error Counter reaches its max value, PRBS checker will stop counting.

When PRBS checker is enabled, DP83822 will check PRBS data received.

When enabled, receive path internal clock (RX_CLK) is delayed by 3.5ns relative to recieve data. When disabled, data and clock are in align mode.

When enabled, transmit path internal clock (TX_CLK) is delayed by 3.5ns relative to transmit data.

This mode, when enabled, reduces latency since both MAC and PHY are synchronized to the same clock source. This mode can also be used when enabling the PHY Clock Output by connecting the MAC to the PHY Output Clock.

When in RMII Recovered Clock mode, the asynchronous FIFO can be bypassed to reduce the receive path latency within the DP83822.

LED_0 polarity defined by strapping value of this pin. This register allows for override of this strap value.

When Force MDI/X is enabled, receive data is on the TD pair and transmit data is on the RD pair. When disabled, receive data is on the RD pair and transmit data is on the TD pair.

Set this bit to '1' to bypass the LED stretching, the LED reflects the internal value.

When enabled, receiver threshold is lowered to allow for operation with longer cables.

This bit is a duplication of bit[12] in the PHYSTS register (0x0010). Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.

Note: This function is only applicable in 10Base-Te operation.

Note: Writing '1' to bit[15] will lock the counter's value for successive read operation and clear the BIST Error Counter.

Diagnostic Start bit is cleared once Diagnostic Done indication bit is triggered.

This bit is self cleared and has the same effect as Hardware reset pin.

This bit is self cleared and resets all PHY digital circuitry except the registers.

Link Lost, LED remains ON until BMCR register (address 0x0001) is read.

Blink for PRBS Errors, LED remains ON for single error and remains until BICSR1 register (address 0x001B) is cleared.

Bit[4] in Register 0x0027 = 1, Enables 10Base-Te Test Patterns.

Bit[4] in Register 0x0428 = 1, Enables 100Base-TX Test Modes

Bits[3:0] select the 10Base-Te test pattern, as follows:

100Base-TX Test Mode is determined by bits {[5] in register 0x0428, [3:0] in register 0x0027}. The bits determine the number of 0's to follow a '1'.

Note 1: To reconfigure the 100Base-TX Test Mode, bit[4] must be cleared in register 0x0428 and then reset to '1' to configure the new pattern.

Note 2: When performing 100Base-TX or 10Base-Te tests modes, the speed must be forced using the Basic Mode Control Register (BMCR), address 0x0000.

When enabled, TX_CLK phase shift is according to the value written to TX Clock Phase Shift Value (bits[4:0]).

Example: If the value of the register is 0x0002, writing 0x0009 to this register will shift TX_CLK by 28ns. (4 times 7ns)

When enabled, the TDR mechanism is looking for reflection on the other pair to check for shorts between pairs.

When enabled, TDR on TD pair will not be executed.

When enabled, TDR on RD pair will not be executed.

When enabled, 100Base-TX Idle Pattern is determined by bit[5] in register 0x0428 and bits[3:0] in register 0x0027.

Note: If set, the DP83822 enters into deep power down mode. Deep power down mode requires that IEEE Power Down be enabled first by either register access (set bit[11] = '1' in register 0x0000) or using INT/PWDN pin.

Note:

Link Lost, LED remains ON until BMCR register (address 0x0001) is read.

Blink for PRBS Errors, LED remains ON for single error and remains until BICSR1 register (address 0x001B) is cleared.

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

When set to Active HIGH, Link drop will occur if SD pin senses a LOW state (SD = '0').

When set to Active LOW, Link drop will occur if SD pin senses a HIGH state (SD = '1').

Note: To enable 100Base-FX Signal Detection on LED_1 (pin #24), strap SD_EN = '1'

Please refer to the strap section in the datasheet for information regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap Mode and do not reflect the same bit sequence that is defined in the strap section of the datasheet.

Please refer to the strap section in the datasheet for information regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap Mode and do not reflect the same bit sequence that is defined in the strap section of the datasheet.

When enabled, bit[9] in this register determines state of LED_1.

When enabled, bit[5] in this register determines state of RX_D3.

If Magic Packet has Bad CRC there will be no indication (status, interrupt, GPIO) when enabled.

When enabling WoL, this bit is automatically set to WoL Interrupt.

Allows for EEE Advertisment during Auto-Negotiation to be determined by bit[0] in register 0x04D1 rather than the Next Page Registers (Register 0x003C and Register 0x003D in MMD7).

When enabled, Auto-Negotiation will negotiate to EEE as defined by register 0x003C and register 0x003D in MMD7.

When disabled, register 0x0014 in MMD3, register 0x003C and register 0x003D in MMD7 are ignored.

Bit should be written to 0 (irrespective of strap used) to disable EEE.