米6体育平台手机版

ZHCSFD6G july 2016 – august 2023 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RHB|32

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.16 Timing Requirements, RGMII

See ⁽¹⁾⁽⁵⁾.

PARAMETER		MIN	TYP	MAX	UNIT
SkewT	Data to Clock output Skew (at Transmitter)⁽²⁾	–500	0		ps
SkewR	Data to Clock input Skew (at Receiver)⁽²⁾	1	1.8		ns
SetupT	Data to Clock output Setup (at Transmitter - integrated delay)⁽³⁾	1.2	2		ns
HoldT	Data to Clock output Hold (at Transmitter - integrated delay)⁽³⁾	1.2	2		ns
SetupR	Data to Clock input Setup (at Receiver - integrated delay)⁽³⁾	1	2		ns
HoldR	Data to Clock input Hold (at Receiver - integrated delay)⁽³⁾	1	2		ns
Tcyc_10	Clock Cycle Duration 10 Mbps	360	400	440	ns
Tcyc_100	Clock Cycle Duration 100 Mbps	36	40	44	ns
Duty_T	Duty Cycle for 10/100 Mbps⁽⁴⁾	40%	50%	60%
Tr / Tf	Rise / Fall Time (20-80%)			750	ps

(1) Ensured by production test, characterization or design.

(2) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.

(3) Device may operate with or without internal delay.

(4) The duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.

(5) See Figure 7-11 and Figure 7-12.