The DP83826 incorporates the reduced media-independent interface (RMII) as specified in the RMII specification v1.2. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3 MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83826 offers two types of RMII operations: RMII Slave and RMII Master. In RMII Master operation, the DP83826 operates from either a 25-MHz CMOS-level oscillator connected to XI pin, a 25-MHz crystal connected across XI and XO pins. A 50-MHz output clock referenced from DP83826 can be connected to the MAC. In RMII Slave operation, the DP83826 operates from a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC. Alternatively, in RMII slave mode, the PHY can operate from a 50-MHz clock provided by the Host MAC

The RMII specification has the following characteristics:

• Supports 100BASE-TX and 10BASE-Te
• Single clock reference sourced from the MAC to PHY (or from an external source)
• Provides independent 2-bit wide transmit and receive data paths
• Uses CMOS signal levels, the same levels as the MII interface

In this mode, data transfers are 2 bits for every clock cycle using the internal 50-MHz reference clock for both transmit and receive paths.

The RMII signals are summarized below:

Figure 9-5 RMII Slave Signaling

Figure 9-6 RMII Master Signaling

Data on TX_D[1:0] are latched at the PHY with reference to the 50 MHz-clock in RMII master mode and slave mode. Data on RX_D[1:0] is provided in reference to 50-MHz clock.

In addition, CRX_DV can be configured as RX_DV signal. It allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication.