ZHCSAB9E September   2012  – June 2019 DP83848-EP

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
      1.      典型系统图
  2. 2 修订历史记录
  3. 3 Pin Configuration and Functions
    1. 3.1 Package Pin Assignments
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 DC Specifications
      1. 4.5.1 Electrical Characteristics
    6. 4.6 AC Specifications
      1. 4.6.1  Power Up Timing
      2. 4.6.2  Reset Timing
      3. 4.6.3  MII Serial Management Timing
      4. 4.6.4  100-Mbps MII Transmit Timing
      5. 4.6.5  100-Mbps MII Receive Timing
      6. 4.6.6  100BASE-TX Transmit Packet Latency Timing
      7. 4.6.7  100BASE-TX Transmit Packet Deassertion Timing
      8. 4.6.8  100BASE-TX Transmit Timing (tR/F and Jitter)
      9. 4.6.9  100BASE-TX Receive Packet Latency Timing
      10. 4.6.10 100BASE-TX Receive Packet Deassertion Timing
      11. 4.6.11 10-Mbps MII Transmit Timing
      12. 4.6.12 10-Mbps MII Receive Timing
      13. 4.6.13 10-Mbps Serial Mode Transmit Timing
      14. 4.6.14 10-Mbps Serial Mode Receive Timing
      15. 4.6.15 10BASE-T Transmit Timing (Start of Packet)
      16. 4.6.16 10BASE-T Transmit Timing (End of Packet)
      17. 4.6.17 10BASE-T Receive Timing (Start of Packet)
      18. 4.6.18 10BASE-T Receive Timing (End of Packet)
      19. 4.6.19 10-Mbps Heartbeat Timing
      20. 4.6.20 10-Mbps Jabber Timing
      21. 4.6.21 10BASE-T Normal Link Pulse Timing
      22. 4.6.22 Auto-Negotiation Fast Link Pulse (FLP) Timing
      23. 4.6.23 100BASE-TX Signal Detect Timing
      24. 4.6.24 100-Mbps Internal Loopback Timing
      25. 4.6.25 10-Mbps Internal Loopback Timing
      26. 4.6.26 RMII Transmit Timing
      27. 4.6.27 RMII Receive Timing
      28. 4.6.28 Isolation Timing
      29. 4.6.29 25MHz_OUT Timing
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Auto-Negotiation
        1. 5.3.1.1 Auto-Negotiation Pin Control
        2. 5.3.1.2 Auto-Negotiation Register Control
        3. 5.3.1.3 Auto-Negotiation Parallel Detection
        4. 5.3.1.4 Auto-Negotiation Restart
        5. 5.3.1.5 Enabling Auto-Negotiation via Software
        6. 5.3.1.6 Auto-Negotiation Complete Time
      2. 5.3.2 Auto-MDIX
      3. 5.3.3 LED Interface
        1. 5.3.3.1 LEDs
        2. 5.3.3.2 LED Direct Control
      4. 5.3.4 Internal Loopback
      5. 5.3.5 BIST
      6. 5.3.6 Energy Detect Mode
    4. 5.4 Device Functional Modes
      1. 5.4.1 MII Interface
        1. 5.4.1.1 Nibble-wide MII Data Interface
        2. 5.4.1.2 Collision Detect
        3. 5.4.1.3 Carrier Sense
      2. 5.4.2 Reduced MII Interface
        1. 5.4.2.1 10 Mb Serial Network Interface (SNI)
      3. 5.4.3 802.3u MII Serial Management Interface
        1. 5.4.3.1 Serial Management Register Access
        2. 5.4.3.2 Serial Management Access Protocol
        3. 5.4.3.3 Serial Management Preamble Suppression
      4. 5.4.4 PHY Address
        1. 5.4.4.1 MII Isolate Mode
      5. 5.4.5 Half Duplex vs Full Duplex
      6. 5.4.6 Reset Operation
        1. 5.4.6.1 Hardware Reset
        2. 5.4.6.2 Software Reset
    5. 5.5 Programming
      1. 5.5.1 Architecture
        1. 5.5.1.1 100BASE-TX Transmitter
          1. 5.5.1.1.1 Code-Group Encoding and Injection
          2. 5.5.1.1.2 Scrambler
          3. 5.5.1.1.3 NRZ to NRZI Encoder
          4. 5.5.1.1.4 Binary to MLT-3 Convertor
        2. 5.5.1.2 100BASE-TX Receiver
          1. 5.5.1.2.1  Analog Front End
          2. 5.5.1.2.2  Digital Signal Processor
            1. 5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control
            2. 5.5.1.2.2.2 Base Line Wander Compensation
          3. 5.5.1.2.3  Signal Detect
          4. 5.5.1.2.4  MLT-3 to NRZI Decoder
          5. 5.5.1.2.5  NRZI to NRZ
          6. 5.5.1.2.6  Serial to Parallel
          7. 5.5.1.2.7  Descrambler
          8. 5.5.1.2.8  Code-group Alignment
          9. 5.5.1.2.9  4B/5B Decoder
          10. 5.5.1.2.10 100BASE-TX Link Integrity Monitor
          11. 5.5.1.2.11 Bad SSD Detection
        3. 5.5.1.3 10BASE-T Transceiver Module
          1. 5.5.1.3.1  Operational Modes
            1. 5.5.1.3.1.1 Half Duplex Mode
            2. 5.5.1.3.1.2 Full Duplex Mode
          2. 5.5.1.3.2  Smart Squelch
          3. 5.5.1.3.3  Collision Detection and SQE
          4. 5.5.1.3.4  Carrier Sense
          5. 5.5.1.3.5  Normal Link Pulse Detection and Generation
          6. 5.5.1.3.6  Jabber Function
          7. 5.5.1.3.7  Automatic Link Polarity Detection and Correction
          8. 5.5.1.3.8  Transmit and Receive Filtering
          9. 5.5.1.3.9  Transmitter
          10. 5.5.1.3.10 Receiver
    6. 5.6 Memory
      1. 5.6.1 Register Definition
        1. 5.6.1.1 Basic Mode Control Register (BMCR)
        2. 5.6.1.2 Basic Mode Status Register (BMSR)
        3. 5.6.1.3 PHY Identifier Register #1 (PHYIDR1)
        4. 5.6.1.4 PHY Identifier Register #2 (PHYIDR2)
        5. 5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)
        6. 5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
        8. 5.6.1.8 Auto-Negotiate Expansion Register (ANER)
        9. 5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
      2. 5.6.2 Extended Registers
        1. 5.6.2.1  PHY Status Register (PHYSTS)
        2. 5.6.2.2  MII Interrupt Control Register (MICR)
        3. 5.6.2.3  MII Interrupt Status and Miscellaneous Control Register (MISR)
        4. 5.6.2.4  False Carrier Sense Counter Register (FCSCR)
        5. 5.6.2.5  Receiver Error Counter Register (RECR)
        6. 5.6.2.6  100 Mbps PCS Configuration and Status Register (PCSR)
        7. 5.6.2.7  RMII and Bypass Register (RBR)
        8. 5.6.2.8  LED Direct Control Register (LEDCR)
        9. 5.6.2.9  PHY Control Register (PHYCR)
        10. 5.6.2.10 10Base-T Status/Control Register (10BTSCR)
        11. 5.6.2.11 CD Test and BIST Extensions Register (CDCTRL1)
        12. 5.6.2.12 Energy Detect Control (EDCR)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
        1. 6.2.1.1 TPI Network Circuit
        2. 6.2.1.2 Clock IN (X1) Requirements
        3. 6.2.1.3 Power Feedback Circuit
        4. 6.2.1.4 Power Down and Interrupt
          1. 6.2.1.4.1 Power Down Control Mode
          2. 6.2.1.4.2 Interrupt Mechanisms
        5. 6.2.1.5 Magnetics
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 MAC Interface (MII/RMII)
        2. 6.2.2.2 Termination Requirement
        3. 6.2.2.3 Recommended Maximum Trace Length
        4. 6.2.2.4 Calculating Impedance
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 PCB Layout Considerations
      2. 8.1.2 PCB Layer Stacking
    2. 8.2 Layout Example
    3. 8.3 Thermal Vias Recommendation
  9. 9 器件和文档支持
    1. 9.1 文档支持
      1. 9.1.1 相关文档
    2. 9.2 Community Resources
    3. 9.3 商标
    4. 9.4 静电放电警告
    5. 9.5 Export Control Notice
    6. 9.6 Glossary
  10. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.6 Memory

Table 5-7 Register Map

OFFSET ACCESS TAG DESCRIPTION
HEX DECIMAL
00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX
08h-Fh 8-15 RW RESERVED RESERVED
EXTENDED REGISTERS
10h 16 RO PHYSTS PHY Status Register
11h 17 RW MICR MII Interrupt Control Register
12h 18 RO MISR MII Interrupt Status Register
13h 19 RW RESERVED RESERVED
14h 20 RO FCSCR False Carrier Sense Counter Register
15h 21 RO RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RBR RMII and Bypass Register
18h 24 RW LEDCR LED Direct Control Register
19h 25 RW PHYCR PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL1 CD Test Control Register and BIST Extensions Register
1Ch 28 RW RESERVED RESERVED
1Dh 29 RW EDCR Energy Detect Control Register
1Eh-1Fh 30-31 RW RESERVED RESERVED

Table 5-8 Register Table

REGISTER NAME ADDRESS TAG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0
Basic Mode Control Register 00h BMCR Reset Loop- back Speed Selection Auto- Neg Enable Power Down Isolate Restart Auto- Neg Duplex Mode Collision Test Re- served Re- served Re- served Re- served Re- served Re- served Re- served
Basic Mode Status Register 01h BMSR 100Base -T4 100Base -TX FDX 100Base -TX HDX 10Base- T FDX 10Base- T HDX Re- served Re- served Re- served Re- served MF Pre- amble Sup- press Auto- Neg Com- plete Remote Fault Auto- Neg Ability Link Status Jabber Detect Extend- ed Capa- bility
PHY Identifier Register 1 02h PHYIDR 1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB
PHY Identifier Register 2 03h PHYIDR 2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL VNDR_ MDL MDL_ REV MDL_ REV MDL_ REV MDL_ REV
Auto-Negotiation Advertise-ment Register 04h ANAR Next Page Ind Re- served Remote Fault Re- served ASM_ DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Selection Protocol Selection Protocol Selection Protocol Selection Protocol Selection
Auto-Negotiation Link Partner Ability Register (Base Page) 05h ANLPAR Next Page Ind ACK Remote Fault Re- served ASM_ DIR PAUSE T4 TX_FD TX 10_FD 10 Protocol Selection Protocol Selection Protocol Selection Protocol Selection Protocol Selection
Auto-Negotiation Link Partner Ability Register Next Page 05h AN- LPARNP Next Page Ind ACK Mes- sage Page ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code
Auto-Negotiation Expansion Register 06h ANER Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served PDF LP_NP_ ABLE NP_ ABLE PAGE_ RX LP_AN_ ABLE
Auto-Negotiation Next Page TX Register 07h ANNPTR Next Page Ind Re- served Message Page ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
Reserved 08-0fh Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served
EXTENDED REGISTERS
PHY Status Register 10h PHYSTS Re- served MDI-X mode Rx Err Latch Polarity Status False Carrier Sense Signal Detect Descram Lock Page Receive MII Inter- rupt Remote Fault Jabber Detect Auto- Neg Com- plete Loop- back Status Duplex Status Speed Status Link Status
MII Interrupt Control Register 11h MICR Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served TINT INTEN INT_OE
MII Interrupt Status and Misc. Control Register 12h MISR Re- served ED_INT LINK_ INT SPD_ INT DUP_ INT ANC_ INT FHF_ INT RHF_ INT Re- served UNMSK_ ED UNMSK_ LINK UNMSK_ JAB UNMSK_ RF UNMSK_ ANC UNMSK_ FHF UNMSK_ RHF
Reserved 13h Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served
False Carrier Sense Counter Register 14h FCSCR Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT
Receive Error Counter Register 15h RECR Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served RXER- CNT RXER- CNT RXER- CNT RXER- CNT RXER- CNT RXER- CNT RXER- CNT RXER- CNT
PCS Sub-Layer Configura-tion and Status Register 16h PCSR Re- served Re- served Re- served BYP_4B 5B Re- served TQ_EN SD_FOR CE_PMA SD_ OPTION DESC_ TIME Re- served FORCE_ 100_OK Re- served Re- served NRZI_ BYPASS SCRAM_ BYPASS DE SCRAM_ BYPASS
RMII and Bypass Register 17h RBR Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served RMII_ MODE RMII_ REV1_0 RX_OVF _STS RX_UNF _STS RX_RD_ PTR[1] RX_RD_ PTR[0]
LED Direct Control Register 18h LEDCR Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served DRV_SP DLED DRV_LN KLED DRV_AC TLED SPDLED LNKLED ACTLED
PHY Control Register 19h PHYCR MDIX_EN FORCE_ MDIX PAUSE_ RX PAUSE_ TX BIST_fe PSR_15 BIST_ STATUS BIST_ START BP_ STRE- TCH LED_ CNFG[1] LED_ CNFG[0] PHY ADDR PHY ADDR PHY ADDR PHY ADDR PHY ADDR
10Base-T Status/ Control Register 1Ah 10BT_S ERIAL 10BT_S ERIAL REJECT 100 BASE T ERROR RANGE ERROR RANGE SQUE- LCH SQUE- LCH SQUE- LCH LOOPBA CK_10_ DIS LP_DIS FORC_ LINK_10 Re- served POLARI- TY Re- served Re- served HEART_ DIS JABBER _DIS
CD Test Control and BIST Extensions Register 1Bh CDCTRL 1 BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT BIST_ ERROR _COUNT Re- served Re- served BIST_ CONT_ MODE CDPattE N_10 Re- served 10Meg_ Patt_ Gap CDPatt- Sel CDPatt- Sel
Reserved 1Ch Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served
Energy Detect Control Register 1Dh EDCR ED_EN ED_ AUTO_ UP ED_ AUTO_ DOWN ED_ MAN ED_ BURST_ DIS ED_ PWR_ STATE ED_ERR _MET ED_ DATA_ MET ED_ERR _COUNT ED_ERR _COUNT ED_ERR _COUNT ED_ERR _COUNT ED_ DATA_ COUNT ED_ DATA_ COUNT ED_ DATA_ COUNT ED_ DATA_ COUNT
Reserved 1Eh-1Fh Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served Re- served
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