5.3.1.1 Auto-Negotiation Pin Control

The state of AN0 determines the specific mode advertised by the DP83848Q-Q1 as given in Table 5-1. This pin allows configuration options to be selected without requiring internal register access.

The state of AN0 upon power-up/reset, determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or reset can be changed at any time by writing to the Basic Mode Control Register (BMCR) at address 0x00h.

5.3.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83848Q-Q1 transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:

1. 100BASE-TX Full Duplex (Highest Priority)
2. 100BASE-TX Half Duplex
3. 10BASE-T Full Duplex
4. 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is disabled, the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved.

The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848Q-Q1 (only the 100BASE-T4 bit is not set because the DP83848Q-Q1 does not support that function).

The BMSR also provides status on:

• Whether or not Auto-Negotiation is complete
• Whether or not the Link Partner is advertising that a remote fault has occurred
• Whether or not valid link has been established
• Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the DP83848Q-Q1 . All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the technology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 0x05h is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:

• Whether or not a Parallel Detect Fault has occurred
• Whether or not the Link Partner supports the Next Page function
• Whether or not the DP83848Q-Q1 supports the Next Page function
• Whether or not the current page being exchanged by Auto-Negotiation has been received
• Whether or not the Link Partner supports Auto-Negotiation

5.3.1.3 Auto-Negotiation Parallel Detection

The DP83848Q-Q1 supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel Detection requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the Link Partner does not support Auto-Negotiation but is transmitting link signals that the 100BASE-TX or 10BASE-T PMAs recognize as valid link signals.

If the DP83848Q-Q1 completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by reading a zero in the Link Partner Auto-Negotiation Able bit once the Auto-Negotiation Complete bit is set. If configured for parallel detect mode and any condition other than a single good link occurs then the parallel detect fault bit will be set.

5.3.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart Auto-Negotiation) of the BMCR to one. If the mode configured by a successful Auto-Negotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a management agent, will cause the DP83848Q-Q1 to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83848Q-Q1 will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.

5.3.1.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83848Q-Q1 has been initialized upon power-up as a non-auto-negotiating device (forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register (BMCR) must first be cleared and then set for any Auto-Negotiation function to take effect.

5.3.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, Auto-Negotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation.

Table 5-2 LED Mode Selection

5.3.3.1 LEDs

Because the Auto-Negotiation (AN) strap option shares the LED output pin, the external components required for strapping and LED usage must be considered in order to avoid contention.

Specifically, when the LED output is used to drive the LED directly, the active state of the output driver is dependent on the logic level sampled by the AN0 input upon power-up/reset. For example, if the AN0 input is resistively pulled low then the output will be configured as an active high driver. Conversely, if the AN0 input is resistively pulled high, then the output will be configured as an active low driver.

Refer to Figure 5-1 for an example of an AN0 connection to external components. In this example, the AN0 strapping results in Auto-Negotiation enabled with 10/100 Half/Full-Duplex advertised .

The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins.

Figure 5-1 AN0 Strapping and LED Loading Example

5.3.3.2 LED Direct Control

The DP83848Q-Q1 provides another option to directly control the LED output through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to the LED.

5.4.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various control and status signals, allow for the simultaneous exchange of data between the DP83848Q-Q1 and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both a transmit and receive operation occur simultaneously.

5.4.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.

If the DP83848Q-Q1 is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision.

If a collision occurs during a receive operation, it is immediately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII.

5.4.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch function during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

Table 5-3 Supported Packet Sizes at ±50 ppm ±k100 ppm For Each Clock

5.4.3.1 Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and MDIO. The DP83848Q-Q1 implements all the required MII registers as well as several optional registers. These registers are fully described in Section 5.6.

5.4.3.2 Serial Management Access Protocol

The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 5-4.

The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83848Q-Q1 with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected.

The DP83848Q-Q1 waits until it has received this preamble sequence before responding to any other transaction. Once the DP83848Q-Q1 serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred.

The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83848Q-Q1 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 5-2 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83848Q-Q1 (PHY) for a typical register read access.

For write transactions, the station management entity writes data to the addressed DP83848Q-Q1 thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 5-3 shows the timing relationship for a typical MII register write access.

Figure 5-2 Typical MDC/MDIO Read Operation

Figure 5-3 Typical MDC/MDIO Write Operation

5.4.3.3 Serial Management Preamble Suppression

The DP83848Q-Q1 supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction.

The DP83848Q-Q1 requires a single initialization sequence of 32 bits of preamble following hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported.

While the DP83848Q-Q1 requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in the IEEE 802.3u specification.

Table 5-5 PHY Address Mapping

5.4.4.1 MII Isolate Mode

The DP83848Q-Q1 can be put into MII Isolate mode by writing to bit 10 of the BMCR register or by strapping in Physical Address 0. It should be noted that selecting Physical Address 0 via an MDIO write to PHYCR will not put the device in the MII isolate mode.

When in the MII isolate mode, the DP83848Q-Q1 does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83848Q-Q1 will continue to respond to all management transactions.

While in Isolate mode, the PMD output pair will not transmit packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83848Q-Q1 can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848Q-Q1 is in Isolate mode.

5.4.6.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and the hardware configuration values will be re-latched into the device (similar to the power-up/reset operation).

5.4.6.2 Software Reset

A software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register (BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has concluded is approximately 1 µs.

A software reset will reset the device such that all the registers will be re-initialized to default values and the hardware configuration values will be re-latched into the device. Software driver code must wait 3 µs following a software reset before allowing further serial MII operations with the DP83848Q-Q1

5.5.1.1 100BASE-TX Transmitter

The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the magnetics. The block diagram in Figure 5-5. provides an overview of each functional block within the 100BASE-TX transmit section.

The Transmitter section consists of the following functional blocks:

• Code-group Encoder and Injection block
• Scrambler block (bypass option)
• NRZ to NRZI encoder block
• Binary to MLT-3 converter / Common Driver

The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83848Q-Q1 implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24.

Figure 5-5 100BASE-TX Transmit Block Diagram

5.5.1.2 100BASE-TX Receiver

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MII. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC coupling magnetics.

See Figure 5-6 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

• Analog Front End
• Digital Signal Processor
• Signal Detect
• MLT-3 to Binary Decoder
• NRZI to NRZ Decoder
• Serial to Parallel
• Descrambler
• Code Group Alignment
• 4B/5B Decoder
• Link Integrity Monitor
• Bad SSD Detection

5.5.1.2.2 Digital Signal Processor

The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.

Figure 5-6 100BASE-TX Receive Block Diagram

5.5.1.2.2.1 Digital Adaptive Equalization and Gain Control

When transmitting data at high speeds over copper twisted-pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted-pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission.

To ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. The compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length.

The DP83848Q-Q1 uses an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’

The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery.

The curves given in Figure 5-8 illustrate attenuation at certain frequencies for given cable lengths. This is derived from the worst case frequency vs. attenuation figures as specified in the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit.

Figure 5-7 EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 Meters of CAT 5 Cable

5.5.1.2.2.2 Base Line Wander Compensation

Figure 5-8 100BASE-TX BLW Event

The DP83848Q-Q1 is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern.

BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (that is, copper wire).

BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially serious BLW.

The digital oscilloscope plot provided in Figure 5-9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet loss.

5.5.1.2.7 Descrambler

A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations:

Equation 1.

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups.

In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization.

5.5.1.3 10BASE-T Transceiver Module

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface because this is integrated inside the DP83848Q-Q1 . This section focuses on the general 10BASE-T system level operation.

5.5.1.3.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848Q-Q1 implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted-pair inputs (see Figure 5-9).

The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection.

Figure 5-9 10BASE-T Twisted-Pair Smart Squelch Operation

5.6.1.1 Basic Mode Control Register (BMCR)

5.6.1.2 Basic Mode Status Register (BMSR)

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848Q-Q1 . The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. TI's IEEE assigned OUI is 080017h.

5.6.1.3 PHY Identifier Register #1 (PHYIDR1)

5.6.1.4 PHY Identifier Register #2 (PHYIDR2)

5.6.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation.

5.6.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported.

5.6.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)

5.6.1.8 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

5.6.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

5.6.2.1 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed information.

5.6.2.2 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification.

5.6.2.3 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

5.6.2.4 100 Mb/s PCS Configuration and Status Register (PCSR)

This register contains control and status information for the 100BASE Physical Coding Sublayer.

5.6.2.5 RMII and Bypass Register (RBR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.

5.6.2.6 LED Direct Control Register (LEDCR)

This register provides the ability to directly control the LED output. It does not provide read access to the LED.

5.6.2.7 PHY Control Register (PHYCR)

This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status.

5.6.2.8 10 Base-T Status/Control Register (10BTSCR)

This register is used for control and status for 10BASE-T device operation.

5.6.2.9 CD Test and BIST Extensions Register (CDCTRL1)

This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function.

5.6.2.10 Energy Detect Control (EDCR)

This register provides control and status for the Energy Detect function.