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ZHCSE02C March 2011 – March 2015 DP83848Q-Q1

PRODUCTION DATA.

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- MPQF134A

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- QFND447B

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6 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

The device is a physical layer Ethernet transceiver. Typical operating voltage is 3.3 V with power consumption less than 270 mW. When using the device for Ethernet application, it is necessary to meet certain requirements for normal operation of device. Following typical application and design requirements can be used for selecting appropriate component values for DP83848Q-Q1.

6.2 Typical Application

Figure 6-1 Typical Application

6.2.1 Design Requirements

The design requirements for DP83848Q-Q1 are:

Vin = 3.3 V
Vout = Vcc – 0.5 V
Clock input = 25 MHz for MII and 50 MHz for RMII

6.2.1.1 TPI Network Circuit

Figure 6-2 shows the recommended circuit for a 10/100 Mb/s twisted-pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.

Pulse H1102
Pulse H2019
Pulse J0011D21
Pulse J0011D21B

Figure 6-2 10/100-Mb/s Twisted-Pair Interface

6.2.1.2 Clock IN (X1) Requirements

The DP83848Q-Q1 supports an external CMOS level oscillator source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1 and Table 6-2.

Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-4 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, C_L1 and C_L2 should be set at 33 pF, and R₁ should be set at 0 Ω.

Specification for 25-MHz crystal are listed in Table 6-3.

Figure 6-3 Crystal Oscillator Circuit

Table 6-1 25-MHz Oscillator Specification

PARAMETER	MIN	TYP	MAX	UNIT	CONDITION
Frequency		25		MHz
Frequency Tolerance			±50	ppm	Operational Temperature
Frequency Stability			±50	ppm	1 year aging
Rise / Fall Time			6	nsec	20% - 80%
Jitter			800⁽¹⁾	psec	Short term
Jitter			800⁽¹⁾	psec	Long term
Symmetry	40%		60%		Duty Cycle

(1) This limit is provided as a guideline for component selection and not specified by production testing. Refer to SNLA091, PHYTER 100 Base-TX Reference Clock Jitter Tolerance, for details on jitter performance.

Table 6-2 50-MHz Oscillator Specification

PARAMETER	MIN	TYP	MAX	UNIT	CONDITION
Frequency		50		MHz
Frequency Tolerance			±50	ppm	Operational Temperature
Frequency Stability			±50	ppm	Operational Temperature
Rise / Fall Time			6	nsec	20% - 80%
Jitter			800⁽¹⁾	psec	Short term
Jitter			800⁽¹⁾	psec	Long term
Symmetry	40%		60%		Duty Cycle

Table 6-3 25-MHz Crystal Specification

PARAMETER	MIN	TYP	MAX	UNIT	CONDITION
Frequency		25		MHz
Frequency Tolerance			±50	ppm	Operational Temperature
Frequency Stability			±50	ppm	1 year aging
Load Capacitance	25		40	pF

6.2.1.3 Power Feedback Circuit

To ensure correct operation for the DP83848Q-Q1 , parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device.

Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (0.1 µF). See Figure 6-4 below for proper connections.

Figure 6-4 Power Feedback Connection

6.2.1.4 Magnetics

The magnetics have a large impact on the PHY performance as well. While several components are listed below, others may be compatible following the requirements listed in Table 6-4. It is recommended that the magnetics include both an isolation transformer and an integrated common mode choke to reduce EMI. When doing the layout, do not run signals under the magnetics. This could cause unwanted noise crosstalk. Likewise void the planes under discrete magnetics, this will help prevent common mode noise coupling. To save board space and reduce component count, an RJ-45 with integrated magnetics may be used.

Table 6-4 Magnetics Requirements

PARAMETER	TYP	UNIT	CONDITION
Turn Ratio	1:1	—	±2%
Insertion Loss	–1	dB	1 MHz to 100 MHz
Return Loss	–16	dB	1 MHz to 30 MHz
	–12	dB	30 MHz to 60 MHz
	–10	dB	60 MHz to 80 MHz
Differential to Common Rejection Ratio	–30	dB	1 MHz to 50 MHz
Differential to Common Rejection Ratio	–20	dB	50 MHz to 150 MHz
Crosstalk	–35	dB	30 MHz
Crosstalk	–30	dB	60 MHz
Isolation	1500	Vrms	HPOT

6.2.2 Detailed Design Procedure

6.2.2.1 MAC Interface (MII/RMII)

The Media Independent Interface (MII) connects the PHYTER component to the Media Access Controller (MAC). The MAC may in fact be a discrete device, integrated into a microprocessor, CPU or FPGA. On the MII signals, the IEEE specification states the bus should be 68 ohm impedance. For space critical designs, the PHYTER family of products also support Reduced MII (RMII). For additional information on this mode of operation, refer to the AN-1405 DP83848 Single 10/100 Mb/s Ethernet Transceiver Reduced Media Independent Interface (RMII) Mode Application Report (SNLA076).

6.2.2.2 Termination Requirement

To reduce digital signal energy, 50-Ω series termination resistors are recommended for all MII output signals (including RXCLK, TXCLK, and RX Data signals).

6.2.2.3 Recommended Maximum Trace Length

Although RMII and MII are synchronous bus architectures, there are a number of factors limiting signal trace lengths. With a longer trace, the signal becomes more attenuated at the destination and thus more susceptible to noise interference. Longer traces also act as antennas, and if run on the surface layer, can increase EMI radiation. If a long trace is running near and adjacent to a noisy signal, the unwanted signals could be coupled in as crosstalk. TI recommends keeping the signal trace lengths as short as possible. Ideally, keep the traces under 6 inches. Trace length matching, to within 2 inches on the MII or RMII bus is also recommended. Significant differences in the trace lengths can cause data timing issues. As with any high-speed data signal, good design practices dictate that impedance should be maintained and stubs should be avoided throughout the entire data path.

6.2.2.4 Calculating Impedance

Equation 1 through Equation 4 can be used to calculate the differential impedance of the board. For microstrip traces, a solid ground plane is needed under the signal traces. The ground plane helps keep the EMI localized and the trace impedance continuous. Because stripline traces are typically sandwiched between the ground/supply planes, they have the advantage of lower EMI radiation and less noise coupling. The trade off of using strip line is lower propagation speed.

Microstrip Impedance - Single-Ended:

Equation 1. DP83848Q-Q1 equation1_snls341.gif