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ZHCSEC3D October 2015 – November 2022 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

7.9 SGMII Timing

PARAMETER		TEST CONDITIONS ⁽³⁾	MIN	NOM	MAX	UNIT
T1	SGMII Clock Output Duty Cycle		48%		52%
T2	Setup time	See ⁽¹⁾	100			ps
T3	Clock to Data relationship from either edges of the clock to valid data	See ⁽²⁾	250		550	ps
T_R	VOD fall time	20% - 80%	100		200	ps
T_F	VOD rise time	20% - 80%	100		200	ps
T_hold	Hold time	See ⁽¹⁾	100			ps
T_TXLAT	SGMII to MDI Latency	See ⁽⁴⁾		201		ns
T_RXLAT	MDI to SGMII Latency	See ⁽⁴⁾		289		ns

(1) Setup and hold time are measured at 50% of the transition.

(2) T3 is measured at 0 V differential.

(3) Ensured by production test, characterization, or design.

(4) Operating in 1000Base-T