ZHCSDE3G February   2015  – October 2022 DP83867CR , DP83867IR

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     7
    2. 6.1 Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power-Up Timing
    7. 7.7  Reset Timing
    8. 7.8  MII Serial Management Timing
    9. 7.9  RGMII Timing
    10. 7.10 GMII Transmit Timing (1)
    11. 7.11 GMII Receive Timing (1)
    12. 7.12 100-Mbps MII Transmit Timing (1)
    13. 7.13 100-Mbps MII Receive Timing (1)
    14. 7.14 10-Mbps MII Transmit Timing (1)
    15. 7.15 10-Mbps MII Receive Timing (1)
    16. 7.16 DP83867IR/CR Start of Frame Detection Timing
    17. 7.17 Timing Diagrams
    18. 7.18 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 8.3.1.1 Magic Packet Structure
        2. 8.3.1.2 Magic Packet Example
        3. 8.3.1.3 Wake-on-LAN Configuration and Status
      2. 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 8.3.2.1 SFD Latency Variation and Determinism
          1. 8.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 8.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 8.3.2.1.3 100-Mb SFD Variation
      3. 8.3.3 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 MAC Interfaces
        1. 8.4.1.1 Reduced GMII (RGMII)
          1. 8.4.1.1.1 1000-Mbps Mode Operation
          2. 8.4.1.1.2 1000-Mbps Mode Timing
          3. 8.4.1.1.3 10- and 100-Mbps Mode
        2. 8.4.1.2 Gigabit MII (GMII)
        3. 8.4.1.3 Media Independent Interface (MII)
          1. 8.4.1.3.1 Nibble-wide MII Data Interface
          2. 8.4.1.3.2 Collision Detect
          3. 8.4.1.3.3 Carrier Sense
      2. 8.4.2 Serial Management Interface
        1. 8.4.2.1 Extended Address Space Access
          1. 8.4.2.1.1 Write Address Operation
          2. 8.4.2.1.2 Read Address Operation
          3. 8.4.2.1.3 Write (No Post Increment) Operation
          4. 8.4.2.1.4 Read (No Post Increment) Operation
          5. 8.4.2.1.5 Write (Post Increment) Operation
          6. 8.4.2.1.6 Read (Post Increment) Operation
          7. 8.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 8.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 8.4.3 Auto-Negotiation
        1. 8.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 8.4.3.2 Master and Slave Resolution
        3. 8.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 8.4.3.4 Next Page Support
        5. 8.4.3.5 Parallel Detection
        6. 8.4.3.6 Restart Auto-Negotiation
        7. 8.4.3.7 Enabling Auto-Negotiation Through Software
        8. 8.4.3.8 Auto-Negotiation Complete Time
        9. 8.4.3.9 Auto-MDIX Resolution
      4. 8.4.4 Loopback Mode
        1. 8.4.4.1 Near-End Loopback
          1. 8.4.4.1.1 MII Loopback
          2. 8.4.4.1.2 PCS Loopback
          3. 8.4.4.1.3 Digital Loopback
          4. 8.4.4.1.4 Analog Loopback
        2. 8.4.4.2 External Loopback
        3. 8.4.4.3 Far-End (Reverse) Loopback
      5. 8.4.5 BIST Configuration
      6. 8.4.6 Cable Diagnostics
        1. 8.4.6.1 TDR
        2. 8.4.6.2 Energy Detect
        3. 8.4.6.3 Fast Link Detect
        4. 8.4.6.4 Speed Optimization
        5. 8.4.6.5 Mirror Mode
        6. 8.4.6.6 Interrupt
        7. 8.4.6.7 IEEE 802.3 Test Modes
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 LED Operation From 1.8-V I/O VDD Supply
      4. 8.5.4 PHY Address Configuration
      5. 8.5.5 Reset Operation
        1. 8.5.5.1 Hardware Reset
        2. 8.5.5.2 IEEE Software Reset
        3. 8.5.5.3 Global Software Reset
        4. 8.5.5.4 Global Software Restart
      6. 8.5.6 Power-Saving Modes
        1. 8.5.6.1 IEEE Power Down
        2. 8.5.6.2 Deep Power-Down Mode
        3. 8.5.6.3 Active Sleep
        4. 8.5.6.4 Passive Sleep
    6. 8.6 Register Maps
      1. 8.6.1   Basic Mode Control Register (BMCR)
      2. 8.6.2   Basic Mode Status Register (BMSR)
      3. 8.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 8.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 8.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 8.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 8.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 8.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 8.6.10  1000BASE-T Configuration Register (CFG1)
      11. 8.6.11  Status Register 1 (STS1)
      12. 8.6.12  Extended Register Addressing
        1. 8.6.12.1 Register Control Register (REGCR)
        2. 8.6.12.2 Address or Data Register (ADDAR)
      13. 8.6.13  1000BASE-T Status Register (1KSCR)
      14. 8.6.14  PHY Control Register (PHYCR)
      15. 8.6.15  PHY Status Register (PHYSTS)
      16. 8.6.16  MII Interrupt Control Register (MICR)
      17. 8.6.17  Interrupt Status Register (ISR)
      18. 8.6.18  Configuration Register 2 (CFG2)
      19. 8.6.19  Receiver Error Counter Register (RECR)
      20. 8.6.20  BIST Control Register (BISCR)
      21. 8.6.21  Status Register 2 (STS2)
      22. 8.6.22  LED Configuration Register 1 (LEDCR1)
      23. 8.6.23  LED Configuration Register 2 (LEDCR2)
      24. 8.6.24  LED Configuration Register (LEDCR3)
      25. 8.6.25  Configuration Register 3 (CFG3)
      26. 8.6.26  Control Register (CTRL)
      27. 8.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 8.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 8.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 8.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 8.6.31  Configuration Register 4 (CFG4)
      32. 8.6.32  RGMII Control Register (RGMIICTL)
      33. 8.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 8.6.34  100BASE-TX Configuration (100CR)
      35. 8.6.35  Viterbi Module Configuration (VTM_CFG)
      36. 8.6.36  Skew FIFO Status (SKEW_FIFO)
      37. 8.6.37  Strap Configuration Status Register 1 (STRAP_STS1)
      38. 8.6.38  Strap Configuration Status Register 2 (STRAP_STS2)
      39. 8.6.39  BIST Control and Status Register 1 (BICSR1)
      40. 8.6.40  BIST Control and Status Register 2 (BICSR2)
      41. 8.6.41  BIST Control and Status Register 3 (BICSR3)
      42. 8.6.42  BIST Control and Status Register 4 (BICSR4)
      43. 8.6.43  Configuration for Receiver's Equalizer (CRE)
      44. 8.6.44  RGMII Delay Control Register (RGMIIDCTL)
      45. 8.6.45  Configuration of Receiver's LPF (CRLPF)
      46. 8.6.46  Enable Control of Receiver's Equalizer (ECRE)
      47. 8.6.47  PLL Clock-out Control Register (PLLCTL)
      48. 8.6.48  Sync FIFO Control (SYNC_FIFO_CTRL)
      49. 8.6.49  Loopback Configuration Register (LOOPCR)
      50. 8.6.50  DSP Configuration (DSP_CONFIG)
      51. 8.6.51  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      52. 8.6.52  Receive Configuration Register (RXFCFG)
      53. 8.6.53  Receive Status Register (RXFSTS)
      54. 8.6.54  Pattern Match Data Register 1 (RXFPMD1)
      55. 8.6.55  Pattern Match Data Register 2 (RXFPMD2)
      56. 8.6.56  Pattern Match Data Register 3 (RXFPMD3)
      57. 8.6.57  SecureOn Pass Register 2 (RXFSOP1)
      58. 8.6.58  SecureOn Pass Register 2 (RXFSOP2)
      59. 8.6.59  SecureOn Pass Register 3 (RXFSOP3)
      60. 8.6.60  Receive Pattern Register 1 (RXFPAT1)
      61. 8.6.61  Receive Pattern Register 2 (RXFPAT2)
      62. 8.6.62  Receive Pattern Register 3 (RXFPAT3)
      63. 8.6.63  Receive Pattern Register 4 (RXFPAT4)
      64. 8.6.64  Receive Pattern Register 5 (RXFPAT5)
      65. 8.6.65  Receive Pattern Register 6 (RXFPAT6)
      66. 8.6.66  Receive Pattern Register 7 (RXFPAT7)
      67. 8.6.67  Receive Pattern Register 8 (RXFPAT8)
      68. 8.6.68  Receive Pattern Register 9 (RXFPAT9)
      69. 8.6.69  Receive Pattern Register 10 (RXFPAT10)
      70. 8.6.70  Receive Pattern Register 11 (RXFPAT11)
      71. 8.6.71  Receive Pattern Register 12 (RXFPAT12)
      72. 8.6.72  Receive Pattern Register 13 (RXFPAT13)
      73. 8.6.73  Receive Pattern Register 14 (RXFPAT14)
      74. 8.6.74  Receive Pattern Register 15 (RXFPAT15)
      75. 8.6.75  Receive Pattern Register 16 (RXFPAT16)
      76. 8.6.76  Receive Pattern Register 17 (RXFPAT17)
      77. 8.6.77  Receive Pattern Register 18 (RXFPAT18)
      78. 8.6.78  Receive Pattern Register 19 (RXFPAT19)
      79. 8.6.79  Receive Pattern Register 20 (RXFPAT20)
      80. 8.6.80  Receive Pattern Register 21 (RXFPAT21)
      81. 8.6.81  Receive Pattern Register 22 (RXFPAT22)
      82. 8.6.82  Receive Pattern Register 23 (RXFPAT23)
      83. 8.6.83  Receive Pattern Register 24 (RXFPAT24)
      84. 8.6.84  Receive Pattern Register 25 (RXFPAT25)
      85. 8.6.85  Receive Pattern Register 26 (RXFPAT26)
      86. 8.6.86  Receive Pattern Register 27 (RXFPAT27)
      87. 8.6.87  Receive Pattern Register 28 (RXFPAT28)
      88. 8.6.88  Receive Pattern Register 29 (RXFPAT29)
      89. 8.6.89  Receive Pattern Register 30 (RXFPAT30)
      90. 8.6.90  Receive Pattern Register 31 (RXFPAT31)
      91. 8.6.91  Receive Pattern Register 32 (RXFPAT32)
      92. 8.6.92  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      93. 8.6.93  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      94. 8.6.94  Receive Pattern Byte Mask Register 3 (RXFPBM3)
      95. 8.6.95  Receive Pattern Byte Mask Register 4 (RXFPBM4)
      96. 8.6.96  Receive Pattern Control (RXFPATC)
      97. 8.6.97  I/O Configuration (IO_MUX_CFG)
      98. 8.6.98  GPIO Mux Control Register 1 (GPIO_MUX_CTRL1)
      99. 8.6.99  GPIO Mux Control Register 2 (GPIO_MUX_CTRL2)
      100. 8.6.100 GPIO Mux Control Register (GPIO_MUX_CTRL)
      101. 8.6.101 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      102. 8.6.102 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      103. 8.6.103 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      104. 8.6.104 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      105. 8.6.105 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      106. 8.6.106 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      107. 8.6.107 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      108. 8.6.108 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      109. 8.6.109 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      110. 8.6.110 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      111. 8.6.111 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      112. 8.6.112 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      113. 8.6.113 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      114. 8.6.114 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      115. 8.6.115 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      116. 8.6.116 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      117. 8.6.117 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      118. 8.6.118 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      119. 8.6.119 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      120. 8.6.120 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      121. 8.6.121 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      122. 8.6.122 TDR General Status (TDR_GEN_STATUS)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Cable Line Driver
        2. 9.2.1.2 Clock In (XI) Recommendation
        3. 9.2.1.3 Crystal Recommendations
        4. 9.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MAC Interface
          1. 9.2.2.1.1 RGMII Layout Guidelines
          2. 9.2.2.1.2 GMII Layout Guidelines
        2. 9.2.2.2 Media Dependent Interface (MDI)
          1. 9.2.2.2.1 MDI Layout Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
    7. 12.7 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RGZ|48
  • PAP|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.20 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.

Table 8-29 BIST Control Register (BISCR), Address 0x0016
BITBIT NAMEDEFAULTDESCRIPTION
15PRBS_COUNT_MODE0, RWPRBS Continuous Mode:
1 = Continuous mode enabled. When one of the PRBS counters reaches the maximum value, a pulse is generated and the counter starts counting from zero again. This bit must be set for proper PRBS operation.
0 = PRBS continuous mode disabled. PRBS operation is not supported for this setting.
14GEN_PRBS_PACKET0, RWGenerated PRBS Packets:
1 = When the packet generator is enabled, it will generate continuous packets with PRBS data. When the packet generator is disabled, the PRBS checker is still enabled.
0 = When the packet generator is enabled, it will generate a single packet with constant data. PRBS generation and checking is disabled.
13PACKET_GEN_64BIT_MODE0, RWBIST Packet Size:
1 = Transmit 64 byte packets in packet generation mode.
0 = Transmit 1518 byte packets in packet generation mode
12PACKET_GEN_EN0, RWPacket BIST Enable:
1 = Enable packet/PRBS generator
0 = Disable packet/PRBS generator
11:8RESERVED0, RORESERVED: Writes ignored, read as 0.
7REV_LOOP_RX_DATA_CTRL0, RWReverse Loopback Receive Data Control:
This bit may only be set in Reverse Loopback mode.
1 = Send RX packets to MAC in reverse loop
0 = Suppress RX packets to MAC in reverse loop
6MII_LOOP_TX_DATA_CTRL0, RWMII Loopback Transmit Data Control:
This bit may only be set in MII Loopback mode.
1 = Transmit data to MDI in MII loop
0 = Suppress data to MDI in MII loop
5:2LOOPBACK_MODE0, RWLoopback Mode Select:
PCS Loopback must be disabled (Bits [1:0] =00) prior to selecting the loopback mode.
1000: Reverse loop
0100: External loop
0010: Analog loop
0001: Digital loop
1:0PCS_LOOPBACK0, RWPCS Loopback Select:
When configured for 100Base-TX:
11: Loop after MLT3 encoder (full TX/RX path)
10: Loop after scrambler, before MLT3 encoder
01: Loop before scrambler
When configured for 1000Base-T:
x1: Loop before 1000Base-T signal processing.
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