ZHCSDE3G February 2015 – October 2022 DP83867CR , DP83867IR
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
| BIT | BIT NAME | DEFAULT | DESCRIPTION |
|---|---|---|---|
| 15 | RESET | 0, RW/SC | Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is restrapped. |
| 14 | LOOPBACK | 0, RW | Loopback: 1 = Loopback enabled. 0 = Normal operation. The loopback function enables MII transmit data to be routed to the MII receive data path. Setting this bit may cause the descrambler to lose synchronization and produce a 500-µs dead time before any valid data will appear at the MII receive outputs. |
| 13 | SPEED SELECTION LSB | 0, RW | Speed Select (Bits 6, 13): When auto-negotiation is disabled writing to this bit allows the port speed to be selected. 11 = Reserved 10 = 1000 Mbps 1 = 100 Mbps 0 = 10 Mbps |
| 12 | AUTO-NEGOTIATION ENABLE | Strap, RW | Auto-Negotiation Enable: Strap controls initial value at reset. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. |
| 11 | POWER DOWN | 0, RW | Power Down: 1 = Power down. 0 = Normal operation. Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. This bit is ORd with the input from the PWRDOWN_INT pin. When the active low PWRDOWN_INT pin is asserted, this bit will be set. |
| 10 | ISOLATE | 0, RW | Isolate: 1 = Isolates the Port from the MII with the exception of the serial management. 0 = Normal operation. |
| 9 | RESTART AUTO-NEGOTIATION | 0, RW/SC | Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation. |
| 8 | DUPLEX MODE | Strap, RW | Duplex Mode: When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected. 1 = Full Duplex operation. 0 = Half Duplex operation. |
| 7 | COLLISION TEST | 0, RW | Collision Test: 1 = Collision test enabled. 0 = Normal operation. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in response to the deassertion of TX_EN. |
| 6 | SPEED SELECTION MSB | 1, RW | Speed Select: See description for bit 13. |
| 5:0 | RESERVED | 0 0000, RO | RESERVED: Write ignored, read as 0. |