ZHCSDE3G February 2015 – October 2022 DP83867CR , DP83867IR
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
Clause 22 of the IEEE 802.3 specification defines the Media Independent Interface. This interface includes a dedicated receive bus and a dedicated transmit bus. These two data buses, along with various control and status signals, allow for the simultaneous exchange of data between the DP83867 and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10 Mbps operation modes or at 25 MHz to support 100 Mbps operational modes.
The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a transmit clock TX_CLK which runs at either 2.5 MHz or 25 MHz. Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half-Duplex mode. The COL signal asserts as an indication of a collision which can occur during Half-Duplex operation when both a transmit and receive operation occur simultaneously.