The DP83867IRPAP can be set to respond to any of 32 possible PHY addresses via strap pins. DP83867IRRGZ/CRRGZ support 16 addresses. The information is latched into the device at a device power up or hardware reset. Each DP83867 or port sharing an MDIO bus in a system must have a unique physical address. The DP83867IRPAP supports PHY address strapping values 0 (<00000>) through 31 (<11111>). DP83867IRRGZ/CRRGZ support PHY addresses from 0(<0000>) to 16(<1111>).

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other hardware configuration pins, refer to Section 8.5.5.

Based on the default strap configuration of PHY_ADD[4:0], the DP83867 PHY address will initialize to 0x00 without any external strap configuration.

Refer to Figure 8-15 for an example of a PHY address connection to external components. In this example, the pins are configured as follows: RX_D4 = Strap Mode 4, RX_D2 = Strap Mode 3, and RX_D0 = Strap Mode 2. Therefore, the PHY address strapping results in address 11001 (19h).

Figure 8-15 IRPAP PHY Address Strapping Example

Refer to Figure 8-16 for an example of a PHY address connection to external components. In this example, the pins are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address strapping results in address 1001 (09h).

Figure 8-16 RGZ PHY Address Strapping Example