ZHCSDE3G February 2015 – October 2022 DP83867CR , DP83867IR
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
| BIT | BIT NAME | DEFAULT | DESCRIPTION | ||||
|---|---|---|---|---|---|---|---|
| 15 | Fast Link-Up in Parallel Detect | 0, RW | Fast Link-Up in Parallel Detect Mode: 1 = Enable Fast Link-Up time During Parallel Detection 0 = Normal Parallel Detection link establishment In Fast Auto MDI-X this bit is automatically set. | ||||
| 14 | Fast AN Enable | 0, RW | Fast Auto-Negotiation Enable: 1 = Enable Fast Auto-Negotiation mode – The PHY auto-negotiates using Timer setting according to Fast AN Sel bits 0 = Disable Fast Auto-Negotiation mode – The PHY auto-negotiates using normal Timer setting Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. Note: When using this option care must be taken to maintain proper operation of the system. While shortening these timer intervals may not cause problems in normal operation, there are certain situations where this may lead to problems. | ||||
| 13:12 | Fast AN Sel | 0, RW | Fast Auto-Negotiation Select bits: | ||||
| Fast AN Select | Break Link Timer(ms) | Link Fall Inhibit Timer(ms) | Auto-Neg Wait Timer(ms) | ||||
| <00> | 80 | 50 | 35 | ||||
| <01> | 120 | 75 | 50 | ||||
| <10> | 240 | 150 | 100 | ||||
| <11> | NA | NA | NA | ||||
| Adjusting these bits reduces the time it takes to auto-negotiate between two PHYs. In Fast AN mode, both PHYs should be configured to the same configuration. These 2 bits define the duration for each state of the Auto-Negotiation process according to the table above. The new duration time must be enabled by setting Fast AN En - bit 4 of this register. Note: Using this mode in cases where both link partners are not configured to the same Fast Auto-Negotiation configuration might produce scenarios with unexpected behavior. | |||||||
| 11 | Extended FD Ability | 0, RW | Extended Full-Duplex Ability: 1 = Force Full-Duplex while working with link partner in forced 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated in Force 100B-TX, the link is always Full Duplex 0 = Disable Extended Full Duplex Ability. Decision to work in Full Duplex or Half Duplex mode follows IEEE specification. | ||||
| 10 | RESERVED | 0, RO | RESERVED | ||||
| 9 | Robust Auto-MDIX | 0, RW | Robust Auto-MDIX: 1 =Enable Robust Auto MDI/MDIX resolution 0 = Normal Auto MDI/MDIX mode If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force 100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock. | ||||
| 8 | Fast Auto-MDIX | 0, RW | Fast Auto MDI/MDIX: 1 = Enable Fast Auto MDI/MDIX mode 0 = Normal Auto MDI/MDIX mode If both link partners are configured to work in Force 100Base-TX mode (Auto-Negotiation is disabled), this mode enables Automatic MDI/MDIX resolution in a short time. | ||||
| 7 | INT_OE | 0, RW | Interrupt Output Enable: 1 = INTN/PWDNN Pad is an Interrupt Output. 0 = INTN/PWDNN Pad in a Power-Down Input. | ||||
| 6 | FORCE_INTERRUPT | 0, RW | Force Interrupt: 1 = Assert interrupt pin. 0 = Normal interrupt mode. | ||||
| 5:3 | RESERVED | 0, RO | RESERVED: Writes ignored, read as 0. | ||||
| 2 | TDR_FAIL | 0, RO | TDR Failure: 1 = TDR failed. 0 = Normal TDR operation. | ||||
| 1 | TDR_DONE | 1, RO | TDR Done: 1 = TDR has completed. 0 = TDR has not completed. | ||||
| 0 | TDR_START | 0, RW | TDR Start: 1 = Start TDR. 0 = Normal operation | ||||