RX_D

3
RX_M

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV is asserted. A data nibble, RX_D[3:0], is transmitted in MII and RGMII modes. 2 bits; RX_D[1:0], are transmitted in RMII mode. RX_D[3:2] are not used when in RMII mode.

If the PHY is bootstrapped to RMII Master mode, a 50MHz clock reference is automatically outputted on RX_D3. This clock should be fed to the MAC.

RX_M / RX_P: Differential SGMII Data Output. These pins transmit data from the PHY to the MAC. This data is synchronous to the differential SGMII clock output.

RXCLK_M / RXCLK_P: Differential SGMII Clock Output. This signal is a continuous 625MHz clock signal driven by the PHY in 6-wire SGMII mode. (configurable through register access)

RX_D2
RX_P

RX_D1
RXCLK_M

RX_D0
RXCLK_P

Receive Clock: In MII and RGMII modes, the receive clock provides a 25MHz reference clock.

Unused in RMII and SGMII modes

Receive Error: In MII and RMII modes, this pin indicates a receive error symbol has been detected within a received packet. In MII mode, RX_ER is asserted high synchronously to the rising edge of RX_CLK. In RMII mode, RX_ER is asserted high synchronously to the rising edge of the reference clock. This pin is not required to be used by the MAC in MII or RMII because the PHY will automatically corrupt data on a receive error.

Unused in RGMII and SGMII modes

Receive Data Valid: This pin indicates when valid data is presented on RX_D[3:0] for MII mode.

Carrier Sense Data Valid: This pin combines carrier sense and data valid into an asynchronous signal. When CRS_DV is asserted, data is presented on RX_D[1:0] in RMII mode.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Unused in SGMII mode

Transmit Clock: In MII mode, the transmit clock is a 25MHz output and has constant phase referenced to the reference clock. In RGMII mode, this clock is sourced from the MAC layer to the PHY. A 25MHz clock should be provided (not required to have constant phase to the reference clock unless synchronous RGMII is enabled in Section 7.6.15).

Unused in RMII and SGMII modes

Transmit Enable: In MII mode, transmit enable is presented prior to the rising edge of the transmit clock. TX_EN indicates the presence of valid data inputs on TX_D[3:0]. In RMII mode, transmit enable is presented prior to the rising edge of the reference clock. TX_EN indicates the presence of valid data inputs on TX_D[1:0].

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented prior to the falling edge of TX_CLK.

Unused in SGMII mode

Transmit Data: In MII and RGMII modes, the transmit data nibble, TX_D[3:0], is received from the MAC prior to the rising edge of TX_CLK. In RMII mode, TX_D[1:0] is received from the MAC prior to the rising edge of the reference clock. TX_D[3:2] are not used in RMII mode.

TX_M / TX_P: Differential SGMII Data Input. These pins receive data that is transmitted from the MAC to the PHY.

TX_D1
TX_P

TX_D0
TX_M

Transmit Error: In MII mode, this pin indicates a transmit error symbol has been detected within a transmitted packet. TX_ER is received prior to the rising edge of TX_CLK.

Unused in RMII, RGMII and SGMII modes

Management Data Clock: Synchronous clock to the MDIO serial management input and output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25MHz. There is no minimum clock rate.

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires a pullup resistor.

Recommended to use a resistor between 2.2kΩ and 9kΩ.

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event.

Note: Power-on-RESET (POR) Done interrupt is enabled by default. POR Done interrupt can be cleared by reading register Section 7.6.16.

This pin can be configured as an Active-HIGH output using register Section 7.6.9.

Reset: Active-LOW input, which initializes or reinitializes the DP83TC811-Q1. Asserting this pin LOW for at least 1μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Section 7.6 section. All bootstrap pins are resampled upon deassertion of reset.

Enable: Active-HIGH input, which will disable the DP83TC811-Q1 when pulled LOW and power down all internal blocks. Disable state is equivalent to a power-down state.

This pin can be directly tied to VDDIO; enabling the device.

WAKE: Active-HIGH input, which wakes the PHY from SLEEP. Asserting this pin HIGH at power-up will prevent the PHY from going to SLEEP.

This pin can be directly tied to VDDIO to wake the device.

INH: Active-HIGH output, which will be asserted HIGH when the PHY is in SLEEP or DISABLED. This pin is LOW for all other PHY states.

Reference Clock Input (MII / RGMII / SGMII): Reference clock 25MHz crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Input (RMII): Reference clock 50MHz CMOS-level oscillator in RMII Slave mode. Reference clock 25MHz crystal or oscillator in RMII Master mode.

This is a fail-safe pin. When the PHY is not powered, an external oscillator is allowed to be powered and driving into this pin. Fail-safe prevents pin back-driving.

Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.

LED_0: Link Status

LED_1: Link Status and BLINK for TX/RX Activity

Clock Output: 25MHz reference clock

Differential Transmit and Receive: Bidirectional differential signaling configured for 100BASE-T1 operation, IEEE 802.3bw compliant.

Test Clock: Primary clock source for all test logic input and output. This pin is controlled by the testing entity.

This pin can be left unconnected if not used.

Test Data Output: Test results are scanned out.

This pin can be left unconnected if not used.

Test Mode Select: Sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends applying three clock cycles with TMS HIGH to reset JTAG.

This pin can be left unconnected if not used.

Test Data Input: Test data is scanned into the device.

This pin can be left unconnected if not used.