SNLS579A April   2018  – November 2018 DP83TC811S-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Pin Multiplexing
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wake-on-LAN (WoL) Packet Detection
        1. 8.3.1.1 Magic Packet Structure
        2. 8.3.1.2 Magic Packet Example
        3. 8.3.1.3 Wake-on-LAN Configuration and Status
      2. 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
      3. 8.3.3 Diagnostic Tool Kit
        1. 8.3.3.1 Signal Quality Indicator
        2. 8.3.3.2 Electrostatic Discharge Sensing
        3. 8.3.3.3 Time Domain Reflectometry
        4. 8.3.3.4 Temperature and Voltage Sensing
        5. 8.3.3.5 Built-In Self-Test
        6. 8.3.3.6 Loopback Modes
          1. 8.3.3.6.1 xMII Loopback
          2. 8.3.3.6.2 PCS Loopback
          3. 8.3.3.6.3 Analog Loopback
          4. 8.3.3.6.4 Reverse Loopback
      4. 8.3.4 Compliance Test Modes
        1. 8.3.4.1 Test Mode 1
        2. 8.3.4.2 Test Mode 2
        3. 8.3.4.3 Test Mode 4
        4. 8.3.4.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Disable
      4. 8.4.4  Standby
      5. 8.4.5  Normal
      6. 8.4.6  Sleep Request
      7. 8.4.7  Silent
      8. 8.4.8  Sleep
      9. 8.4.9  Low-Power Sleep
      10. 8.4.10 Wake-Up
      11. 8.4.11 State Transitions
        1. 8.4.11.1 State Transition #1 - Standby to Normal
        2. 8.4.11.2 State Transition #2 - Normal to Standby
        3. 8.4.11.3 State Transition #3 - Normal to Sleep Request
        4. 8.4.11.4 State Transition #4 - Sleep Request to Normal
        5. 8.4.11.5 State Transition #5 - Sleep Request to Standby
        6. 8.4.11.6 State Transition #6 - Sleep Request to Silent
        7. 8.4.11.7 State Transition #7 - Silent to Standby
        8. 8.4.11.8 State Transition #8 - Silent to Sleep
      12. 8.4.12 Media Dependent Interface
        1. 8.4.12.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.12.2 Auto-Polarity Detection and Correction
        3. 8.4.12.3 Jabber Detection
        4. 8.4.12.4 Interleave Detection
      13. 8.4.13 MAC Interfaces
        1. 8.4.13.1 Media Independent Interface
        2. 8.4.13.2 Reduced Media Independent Interface
        3. 8.4.13.3 Reduced Gigabit Media Independent Interface
        4. 8.4.13.4 Serial Gigabit Media Independent Interface
      14. 8.4.14 Serial Management Interface
      15. 8.4.15 Direct Register Access
      16. 8.4.16 Extended Register Space Access
      17. 8.4.17 Write Address Operation
        1. 8.4.17.1 MMD1 - Write Address Operation
      18. 8.4.18 Read Address Operation
        1. 8.4.18.1 MMD1 - Read Address Operation
      19. 8.4.19 Write Operation (No Post Increment)
        1. 8.4.19.1 MMD1 - Write Operation (No Post Increment)
      20. 8.4.20 Read Operation (No Post Increment)
        1. 8.4.20.1 MMD1 - Read Operation (No Post Increment)
      21. 8.4.21 Write Operation (Post Increment)
        1. 8.4.21.1 MMD1 - Write Operation (Post Increment)
      22. 8.4.22 Read Operation (Post Increment)
        1. 8.4.22.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1   Register Access Summary
      2. 8.6.2   BMCR Register 0x0000 – Basic Mode Control Register
        1. Table 26. BMCR Field Descriptions
      3. 8.6.3   BMSR Register 0x0001 – Basic Mode Status Register
        1. Table 27. BMSR Field Descriptions
      4. 8.6.4   PHYID1 Register 0x0002 – PHY Identifier Register #1
        1. Table 28. PHYID1 Field Descriptions
      5. 8.6.5   PHYID2 Register 0x0003 – PHY Identifier Register #2
        1. Table 29. PHYID2 Field Descriptions
      6. 8.6.6   SGMII_CFG Register 0x0009 – SGMII Configuration Register
        1. Table 30. SGMII_CFG Field Descriptions
      7. 8.6.7   REGCR Register 0x000D – Register Control Register
        1. Table 31. REGCR Field Descriptions
      8. 8.6.8   ADDAR Register 0x000E – Address/Data Register
        1. Table 32. ADDAR Field Descriptions
      9. 8.6.9   INT_TEST Register 0x0011 – Interrupt Test Register
        1. Table 33. INT_TEST Field Descriptions
      10. 8.6.10  INT_STAT1 Register 0x0012 – Interrupt Status Register #1
        1. Table 34. INT_STAT1 Field Descriptions
      11. 8.6.11  INT_STAT2 Register 0x0013 – Interrupt Status Register #2
        1. Table 35. INT_STAT2 Field Descriptions
      12. 8.6.12  FCSCR Register 0x0014 – False Carrier Sense Counter Register
        1. Table 36. FCSCR Field Descriptions
      13. 8.6.13  RECR Register 0x0015 – Receive Error Count Register
        1. Table 37. RECR Field Descriptions
      14. 8.6.14  BISTCR Register 0x0016 – BIST Control Register
        1. Table 38. BISTCR Field Descriptions
      15. 8.6.15  xMII_CTRL Register 0x0017 – xMII Control Register
        1. Table 39. xMII_CTRL Field Descriptions
      16. 8.6.16  INT_STAT3 Register 0x0018 – Interrupt Status Register #3
        1. Table 40. INT_STAT3 Field Descriptions
      17. 8.6.17  BICTSR1 Register 0x001B – BIST Control and Status Register #1
        1. Table 41. BICTSR1 Field Descriptions
      18. 8.6.18  BICTSR2 Register 0x001C – BIST Control and Status Register #2
        1. Table 42. BICTSR2 Field Description
      19. 8.6.19  TDR Register 0x001E – Time Domain Reflectometry Register
        1. Table 43. TDR Field Descriptions
      20. 8.6.20  PHYRCR Register 0x001F – PHY Reset Control Register
        1. Table 44. PHYRCR Field Descriptions
      21. 8.6.21  LSR Register 0x0133 – Link Status Results Register
        1. Table 45. LSR Field Descriptions
      22. 8.6.22  TDRR Register 0x016B – TDR Results Register
        1. Table 46. TDRR Field Descriptions
      23. 8.6.23  TDRLR1 Register 0x0180 – TDR Location Result Register #1
        1. Table 47. TDRLR1 Field Descriptions
      24. 8.6.24  TDRLR2 Register 0x0181 – TDR Location Result Register #2
        1. Table 48. TDRLR2 Field Descriptions
      25. 8.6.25  TDRPT Register 0x018A – TDR Peak Type Register
        1. Table 49. TDRPT Field Descriptions
      26. 8.6.26  AUTO_PHY Register 0x018B – Autonomous PHY Control Register
        1. Table 50. AUTO_PHY Field Descriptions
      27. 8.6.27  PWRM Register 0x018C – Power Mode Register
        1. Table 51. PWRM Register 0x018C – Power Mode Register
      28. 8.6.28  SNR Register 0x0197 – Signal-to-Noise Ratio Result Register
        1. Table 52. SNR Field Descriptions
      29. 8.6.29  SQI Register 0x0198 – Signal Quality Indication Register
        1. Table 53. SQI Field Descriptions
      30. 8.6.30  LD_CTRL Register 0x0400 – Line Driver Control Register
        1. Table 54. LD_CTRL Field Descriptions
      31. 8.6.31  LDG_CTRL1 Register 0x0401 – Line Driver Gain Control Register #1
        1. Table 55. LDG_CTRL1 Field Descriptions
      32. 8.6.32  SGMII_CTRL1 Register 0x0432 – SGMII Control Register #1
        1. Table 56. SGMII_CTRL1 Field Descriptions
      33. 8.6.33  DLL_CTRL 0x0446 – RGMII DLL Control Register
        1. Table 57. DLL_CTRL Field Descriptions
      34. 8.6.34  ESDS Register 0x0448 – Electrostatic Discharge Status Register
        1. Table 58. ESDS Field Descriptions
      35. 8.6.35  SGMII_AUTO_TIMER Register 0x0456 – SGMII Auto-Negotiation Timer Configuration Register
        1. Table 59. SGMII_AUTO_TIMER Field Descriptions
      36. 8.6.36  SGMII_STAT Register 0x0459 – SGMII Auto-Negotiation Status Register
        1. Table 60. SGMII_STAT Field Descriptions
      37. 8.6.37  LED_CFG1 Register 0x0460 – LED Configuration Register #1
        1. Table 61. LED_CFG1 Field Descriptions
      38. 8.6.38  xMII_IMP_CTRL Register 0x0461 – xMII Impedance Control Register
        1. Table 62. xMII_IMP_CTRL Field Descriptions
      39. 8.6.39  IO_CTRL1 Register 0x0462 – GPIO Control Register #1
        1. Table 63. IO_CTRL1 Field Descriptions
      40. 8.6.40  IO_CTRL2 Register 0x0463 – GPIO Control Register #2
        1. Table 64. IO_CTRL2 Field Descriptions
      41. 8.6.41  STRAP Register 0x0467 – Strap Configuration Register
        1. Table 65. STRAP Field Descriptions
      42. 8.6.42  LED_CFG2 Register 0x0469 – LED Configuration Register #2
        1. Table 66. LED_CFG2 Field Descriptions
      43. 8.6.43  PLR_CFG Register 0x0475 – Polarity Auto-Correction Configuration Register
        1. Table 67. PLR_CFG1 Field Descriptions
      44. 8.6.44  MON_CFG1 Register 0x0480 – Monitor Configuration Register #1
        1. Table 68. MON_CFG1 Field Descriptions
      45. 8.6.45  MON_CFG2 Register 0x0481 – Monitor Configuration Register #2
        1. Table 69. MON_CFG2 Field Descriptions
      46. 8.6.46  MON_CFG3 Register 0x0482 – Monitor Configuration Register #3
        1. Table 70. MON_CFG3 Field Descriptions
      47. 8.6.47  MON_STAT1 Register 0x0483 – Monitor Status Register #1
        1. Table 71. MON_STAT1 Field Descriptions
      48. 8.6.48  MON_STAT2 Register 0x0484 – Monitor Status Register #2
        1. Table 72. MON_STAT2 Field Descriptions
      49. 8.6.49  PCS_CTRL1 Register 0x0485 – PCS Control Register #1
        1. Table 73. PCS_CTRL1 Field Descriptions
      50. 8.6.50  PCS_CTRL2 Register – 0x0486 PCS Control Register #2
        1. Table 74. PCS_CTRL2 Field Descriptions
      51. 8.6.51  LPS_CTRL2 Register 0x0487 – LPS Control Register #2
        1. Table 75. LPS_CTRL2 Register 0x0487 – LPS Control Register #2
      52. 8.6.52  INTER_CFG Register 0x0489 – Interleave Configuration
        1. Table 76. INTER_CFG Field Descriptions
      53. 8.6.53  LPS_CTRL3 Register 0x0493 – LPS Control Register #3
        1. Table 77. LPS_CTRL3 Register 0x0493 – LPS Control Register #3
      54. 8.6.54  JAB_CFG Register 0x0496 – Jabber Configuration Register
        1. Table 78. JAB_CFG Field Descriptions
      55. 8.6.55  TEST_MODE_CTRL Register 0x0497 – Test Mode Control Register
        1. Table 79. TEST_MODE_CTRL Field Descriptions
      56. 8.6.56  WOL_CFG Register 0x04A0 – WoL Configuration Register
        1. Table 80. WOL_CFG Field Descriptions
      57. 8.6.57  WOL_STAT Register 0x04A1 – WoL Status Register
        1. Table 81. WOL_STAT Field Descriptions
      58. 8.6.58  WOL_DA1 Register 0x04A2 – WoL Destination Address Configuration Register #1
        1. Table 82. WOL_DA1 Field Descriptions
      59. 8.6.59  WOL_DA2 Register 0x04A3 – WoL Destination Address Configuration Register #2
        1. Table 83. WOL_DA2 Field Descriptions
      60. 8.6.60  WOL_DA3 Register 0x04A4 – WoL Destination Address Configuration Register #3
        1. Table 84. WOL_DA3 Field Descriptions
      61. 8.6.61  RXSOP1 Register 0x04A5 – Receive Secure-ON Password Register #1
        1. Table 85. RXSOP1 Field Descriptions
      62. 8.6.62  RXSOP2 Register 0x04A6 – Receive Secure-ON Password Register #2
        1. Table 86. RXSOP2 Field Descriptions
      63. 8.6.63  RXSOP3 Register 0x04A7 – Receive Secure-ON Password Register #3
        1. Table 87. RXSOP3 Field Descriptions
      64. 8.6.64  RXPAT1 Register 0x04A8 – Receive Pattern Register #1
        1. Table 88. RXPAT1 Field Descriptions
      65. 8.6.65  RXPAT2 Register 0x04A9 – Receive Pattern Register #2
        1. Table 89. RXPAT2 Field Descriptions
      66. 8.6.66  RXPAT3 Register 0x04AA – Receive Pattern Register #3
        1. Table 90. RXPAT3 Field Descriptions
      67. 8.6.67  RXPAT4 Register 0x04AB – Receive Pattern Register #4
        1. Table 91. RXPAT4 Field Descriptions
      68. 8.6.68  RXPAT5 Register 0x04AC – Receive Pattern Register #5
        1. Table 92. RXPAT5 Field Descriptions
      69. 8.6.69  RXPAT6 Register 0x04AD – Receive Pattern Register #6
        1. Table 93. RXPAT6 Field Descriptions
      70. 8.6.70  RXPAT7 Register 0x04AE – Receive Pattern Register #7
        1. Table 94. RXPAT7 Field Descriptions
      71. 8.6.71  RXPAT8 Register 0x04AF – Receive Pattern Register #8
        1. Table 95. RXPAT8 Field Descriptions
      72. 8.6.72  RXPAT9 Register 0x04B0 – Receive Pattern Register #9
        1. Table 96. RXPAT9 Field Descriptions
      73. 8.6.73  RXPAT10 Register 0x04B1 – Receive Pattern Register #10
        1. Table 97. RXPAT10 Field Descriptions
      74. 8.6.74  RXPAT11 Register 0x04B2 Receive Pattern Register #11
        1. Table 98. RXPAT11 Field Descriptions
      75. 8.6.75  RXPAT12 Register 0x04B3 – Receive Pattern Register #12
        1. Table 99. RXPAT12 Field Descriptions
      76. 8.6.76  RXPAT13 Register 0x04B4 – Receive Pattern Register #13
        1. Table 100. RXPAT13 Field Descriptions
      77. 8.6.77  RXPAT14 Register 0x04B5 – Receive Pattern Register #14
        1. Table 101. RXPAT14 Field Descriptions
      78. 8.6.78  RXPAT15 Register 0x04B6 – Receive Pattern Register #15
        1. Table 102. RXPAT15 Field Descriptions
      79. 8.6.79  RXPAT16 Register 0x04B7 – Receive Pattern Register #16
        1. Table 103. RXPAT16 Field Descriptions
      80. 8.6.80  RXPAT17 Register 0x04B8 – Receive Pattern Register #17
        1. Table 104. RXPAT17 Field Descriptions
      81. 8.6.81  RXPAT18 Register 0x04B9 – Receive Pattern Register #18
        1. Table 105. RXPAT18 Field Descriptions
      82. 8.6.82  RXPAT19 Register 0x04BA Receive Pattern Register #19
        1. Table 106. RXPAT19 Field Descriptions
      83. 8.6.83  RXPAT20 Register 0x04BB – Receive Pattern Register #20
        1. Table 107. RXPAT20 Field Descriptions
      84. 8.6.84  RXPAT21 Register 0x04BC – Receive Pattern Register #21
        1. Table 108. RXPAT21 Field Descriptions
      85. 8.6.85  RXPAT22 Register 0x04BD – Receive Pattern Register #22
        1. Table 109. RXPAT22 Field Descriptions
      86. 8.6.86  RXPAT23 Register 0x04BE – Receive Pattern Register #23
        1. Table 110. RXPAT23 Field Descriptions
      87. 8.6.87  RXPAT24 Register 0x04BF – Receive Pattern Register #24
        1. Table 111. RXPAT24 Field Descriptions
      88. 8.6.88  RXPAT25 Register 0x04C0 – Receive Pattern Register #25
        1. Table 112. RXPAT25 Field Descriptions
      89. 8.6.89  RXPAT26 Register 0x04C1 – Receive Pattern Register #26
        1. Table 113. RXPAT26 Field Descriptions
      90. 8.6.90  RXPAT27 Register 0x04C2 Receive Pattern Register #27
        1. Table 114. RXPAT27 Field Descriptions
      91. 8.6.91  RXPAT28 Register 0x04C3 – Receive Pattern Register #28
        1. Table 115. RXPAT28 Field Descriptions
      92. 8.6.92  RXPAT29 Register 0x04C4 – Receive Pattern Register #29
        1. Table 116. RXPAT29 Field Descriptions
      93. 8.6.93  RXPAT30 Register 0x04C5 – Receive Pattern Register #30
        1. Table 117. RXPAT30 Field Descriptions
      94. 8.6.94  RXPAT31 Register 0x04C6 – Receive Pattern Register #31
        1. Table 118. RXPAT31 Field Descriptions
      95. 8.6.95  RXPAT32 Register 0x04C7 – Receive Pattern Register #32
        1. Table 119. RXPAT32 Field Descriptions
      96. 8.6.96  RXPBM1 Register 0x04C8 – Receive Pattern Byte Mask Register #1
        1. Table 120. RXPBM1 Field Descriptions
      97. 8.6.97  RXPBM2 Register 0x04C9 – Receive Pattern Byte Mask Register #2
        1. Table 121. RXPBM2 Field Descriptions
      98. 8.6.98  RXPBM3 Register 0x04CA – Receive Pattern Byte Mask Register #3
        1. Table 122. RXPBM3 Field Descriptions
      99. 8.6.99  RXPBM4 Register 0x04CB – Receive Pattern Byte Mask Register #4
        1. Table 123. RXPBM4 Field Descriptions
      100. 8.6.100 RXPATC Register 0x04CC – Receive Pattern Control Register
        1. Table 124. RXPATC Field Descriptions
      101. 8.6.101 RXD3CLK Register 0x04E0 – RX_D3 Clock Control Register
        1. Table 125. RXD3CLK Field Descriptions
      102. 8.6.102 LPS_CFG Register 0x04E5 – LPS Configuration Register
        1. Table 126. LPS_CFG Register 0x04E5 – LPS Configuration Register
      103. 8.6.103 PMA_CTRL1 Register 0x0007 – MMD1 PMA Control Register #1
        1. Table 127. PMA_CTRL1 Field Descriptions
      104. 8.6.104 PMA_EXT1 Register 0x000B – MMD1 PMA Extended Ability Register #1
        1. Table 128. PMA_EXT1 Field Descriptions
      105. 8.6.105 PMA_EXT2 Register 0x0012 – MMD1 PMA Extended Ability Register #2
        1. Table 129. PMA_EXT2 Field Descriptions
      106. 8.6.106 PMA_CTRL2 Register 0x0834 – MMD1 PMA Control Register #2
        1. Table 130. PMA_CTRL2 Field Descriptions
      107. 8.6.107 TEST_CTRL Register 0x0836 – MMD1 100BASE-T1 PMA Test Control Register
        1. Table 131. TEST_CTRL Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5.1 Strap Configuration

The DP83TC811S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register access). The strap pins support 4 levels, which are described in greater detail below. Configuration of the device may be done through 4-level strapping or through serial management interface.

NOTE

Because strap pins are functional pins after reset is deasserted, they should not be connected directly to VDDIO or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation.
DP83TC811S-Q1 strap_circuit_snls551.gifFigure 28. Strap Circuit

Table 18. Recommended 4-Level Strap Resistor Ratios(1)(2)

MODE IDEAL RH (kΩ) IDEAL RL (kΩ)
1 OPEN OPEN
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
(1) Strap resistors with 1% tolerance are recommended.
(2) Resistor ratios are only a recommendation. Use the bootstrap threshold values contained within the Electrical Characteristics table for more precise mode selections.

The following table describes the DP83TC811S-Q1 configuration bootstraps:

Table 19. 4-Level Bootstraps

PIN
NAME		 PIN NO. DEFAULT
MODE		 STRAP FUNCTION DESCRIPTION
RX_DV 15 1 MODE PHY_AD[0] PHY_AD[2] PHY_AD: PHY Address ID
1 0 0
2 0 1
3 1 1
4 1 0
RX_ER 14 1 MODE PHY_AD[1] PHY_AD[3] PHY_AD: PHY Address ID
1 0 0
2 0 1
3 1 1
4 1 0
RX_D0 26 1 MODE MAC[0] TEST[0] MAC: MAC Interface Selection

TEST: Test Mode Selection
1 0 0
2 0 1
3 1 1
4 1 0
RX_D1 25 1 MODE MAC[1] TEST[1] MAC: MAC Interface Selection

TEST: Test Mode Selection
1 0 0
2 0 1
3 1 1
4 1 0
RX_D2 24 1 MODE MAC[2] TEST[2] MAC: MAC Interface Selection

TEST: Test Mode Selection
1 0 0
2 0 1
3 1 1
4 1 0
RX_D3 23 1 MODE RESERVED RESERVED RX_D3 must be strapped to MODE 1
1 0 0
Reserved
Reserved
Reserved
LED_0 35 1 MODE MS RESERVED MS: 100BASE-T1 Master & 100BASE-T1 Slave Selection
Note: LED_0 must only be set for bootstrap MODE 1 or MODE 4.
1 0
Reserved
Reserved
4 1
LED_1 6 1 MODE AUTO RESERVED AUTO: Autonomous Disable
Note 1: LED_1 must only be set for bootstrap MODE 1 or MODE 4.
Note 2: Autonomous bootstrap is only active for 100BASE-T1 Master mode PHYs. This bootstrap is ignored when the PHY is bootstrapped for 100BASE-T1 Slave mode operation.
1 0
Reserved
Reserved
4 1

Table 20. 100BASE-T1 Master and 100BASE-T1 Slave Selection Bootstrap

MS DESCRIPTION
0 100BASE-T1 Slave Configuration
1 100BASE-T1 Master Configuration

Table 21. MAC Interface Selection Bootstraps

MAC[2] MAC[1] MAC[0] DESCRIPTION
0 0 0

SGMII (4-wire)
0 0 1 MII
0 1 0 RMII Slave
0 1 1 RMII Master
1 0 0 RGMII (Align Mode)
1 0 1 RGMII (TX Internal Delay Mode)
1 1 0 RGMII (TX and RX Internal Delay Mode)
1 1 1 RGMII (RX Internal Delay Mode)

Table 22. Test Mode Bootstraps

TEST[2] TEST[1] TEST[0] Description
0 0 0 Normal Operation
0 0 1 Test Mode 1
0 1 0 Test Mode 2
0 1 1 RESERVED
1 0 0 Test Mode 4
1 0 1 Test Mode 5
1 1 0 RESERVED
1 1 1 RESERVED

Table 23. PHY Address Bootstraps

PHY_AD[3] PHY_AD[2] PHY_AD[1] PHY_AD[0] DESCRIPTION
0 0 0 0 PHY Address: 0b00000 (0)
0 0 0 1 PHY Address: 0b00001 (1)
0 0 1 0 PHY Address: 0b00010 (2)
0 0 1 1 PHY Address: 0b00011 (3)
0 1 0 0 PHY Address: 0b00100 (4)
0 1 0 1 PHY Address: 0b00101 (5)
0 1 1 0 PHY Address: 0b00110 (6)
0 1 1 1 PHY Address: 0b00111 (7)
1 0 0 0 PHY Address: 0b01000 (8)
1 0 0 1 PHY Address: 0b01001 (9)
1 0 1 0 PHY Address: 0b01010 (10)
1 0 1 1 PHY Address: 0b01011 (11)
1 1 0 0 PHY Address: 0b01100 (12)
1 1 0 1 PHY Address: 0b01101 (13)
1 1 1 0 PHY Address: 0b01110 (14)
1 1 1 1 PHY Address: 0b01111 (15)

Table 24. Autonomous Mode Bootstrap

AUTO DESCRIPTION
0 Autonomous Mode, PHY able to establish link after power-up
1 Managed Mode, PHY must be allowed to establish link after power-up based on register write
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