Digital Loopback will loop back data prior to it exiting the Digital and entering the AFE. Data received from the MAC on the transmit path is brought through the digital block within the PHY where it is then routed back to the MAC through the receive path. The DP83TC813 receive Analog circuitry is configured for isolation to prevent contention.

Enable Loopback

Write register 0x0016 = 0x0104

Enable data generator/checker for MAC side

Write register 0x0619 = 0x1555

Write register 0x0624 = 0x55BF

Check incoming data from MAC side

Data can also be checked internally by reading registers 0x063C, 0x063D, 0x063E

Enable data generator/checker for Cable side

Write register 0x0619 = 0x0557

Write register 0x0624 = 0x55BF

Check data for Cable side

1. Write register 0x0620[1] = 1'b1
2. Read register 0x620
   1. Bit [7:0] = Number of errors bytes received
   2. Bit [8] = PRBS checker lock status on incoming data (1'b1 indicates lock)

Repeat steps 1 and 2 to continously check error status of incoming data stream.

Other system requirements

Data generate by the internal PRBS will be transmitted over the MDI and the MAC interface.