The Serial Gigabit Media Independent Interface (SGMII) provides a means for data transfer between MAC and PHY with significantly less signal pins (4 pins) compared to MII (14 pins), RMII (7 pins) or RGMII (12 pins). SGMII uses low-voltage differential signaling (LVDS) to reduce emissions and improve signal quality.

The DP83TC813 SGMII is capable of operating in 4-wire. SGMII is configurable through hardware bootstraps. In 4-wire operation, two differential pairs are used to transmit and receive data. Clock and data recovery are performed in the MAC and in the PHY.

Because the DP83TC813 operates at 100-Mbps, the 1.25-Gbps rate of the SGMII is excessive. The SGMII specification allows for 100-Mbps operation by replicating each byte within a frame 10 times. Frame elongation takes place above the IEEE 802.3 PCS layer, which prevents the start-of-frame delimiter from appearing more than once.

Because the DP83TC813 only supports 100-Mbps speed, SGMII Auto-Negotitation can be disabled by setting bit[0] = 0b0 in the Register 0x608.

The SGMII signals are summarized in Table 8-14.