ZHCSLL4 December   2021 DP83TC814R-Q1 , DP83TC814S-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Diagnostic Tool Kit
        1. 8.3.1.1 Signal Quality Indicator
        2. 8.3.1.2 Electrostatic Discharge Sensing
        3. 8.3.1.3 Time Domain Reflectometry
        4. 8.3.1.4 Voltage Sensing
        5. 8.3.1.5 BIST and Loopback Modes
          1. 8.3.1.5.1 Data Generator and Checker
          2. 8.3.1.5.2 xMII Loopback
          3. 8.3.1.5.3 PCS Loopback
          4. 8.3.1.5.4 Digital Loopback
          5. 8.3.1.5.5 Analog Loopback
          6. 8.3.1.5.6 Reverse Loopback
      2. 8.3.2 Compliance Test Modes
        1. 8.3.2.1 Test Mode 1
        2. 8.3.2.2 Test Mode 2
        3. 8.3.2.3 Test Mode 4
        4. 8.3.2.4 Test Mode 5
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Down
      2. 8.4.2  Reset
      3. 8.4.3  Standby
      4. 8.4.4  Normal
      5. 8.4.5  Media Dependent Interface
        1. 8.4.5.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 8.4.5.2 Auto-Polarity Detection and Correction
        3. 8.4.5.3 Jabber Detection
        4. 8.4.5.4 Interleave Detection
      6. 8.4.6  MAC Interfaces
        1. 8.4.6.1 Media Independent Interface
        2. 8.4.6.2 Reduced Media Independent Interface
        3. 8.4.6.3 Reduced Gigabit Media Independent Interface
      7. 8.4.7  Serial Management Interface
      8. 8.4.8  Direct Register Access
      9. 8.4.9  Extended Register Space Access
      10. 8.4.10 Write Address Operation
        1. 8.4.10.1 MMD1 - Write Address Operation
      11. 8.4.11 Read Address Operation
        1. 8.4.11.1 MMD1 - Read Address Operation
      12. 8.4.12 Write Operation (No Post Increment)
        1. 8.4.12.1 MMD1 - Write Operation (No Post Increment)
      13. 8.4.13 Read Operation (No Post Increment)
        1. 8.4.13.1 MMD1 - Read Operation (No Post Increment)
      14. 8.4.14 Write Operation (Post Increment)
        1. 8.4.14.1 MMD1 - Write Operation (Post Increment)
      15. 8.4.15 Read Operation (Post Increment)
        1. 8.4.15.1 MMD1 - Read Operation (Post Increment)
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Register Access Summary
      2. 8.6.2 DP83TC814 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Metal Pour
      4. 11.1.4 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
MII TIMING
T1.1 TX_CLK High / Low Time 16 20 24 ns
T1.2 TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK 10 ns
T1.3 TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK 0 ns
T2.1 RX_CLK High / Low Time 16 20 24 ns
T2.2 RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising 10 30 ns
RMII MASTER TIMING
T3.1 RMII Master Clock Period 20 ns
RMII Master Clock Duty Cycle 35 65 %
T3.2 TX_D[1:0], TX_ER, TX_EN Setup to RMII Master Clock 4 ns
T3.3 TX_D[1:0], TX_ER, TX_EN Hold from RMII Master Clock 2 ns
T3.4 RX_D[1:0], RX_ER, CRS_DV Delay from RMII Master Clock rising edge 4 10 14 ns
RMII SLAVE TIMING
T3.1 Input Reference Clock Period 20 ns
Reference Clock Duty Cycle 35 65 %
T3.2 TX_D[1:0], TX_ER, TX_EN Setup to XI Clock rising 4 ns
T3.3 TX_D[1:0], TX_ER, TX_EN Hold from XI Clock rising 2 ns
T3.4 RX_D[1:0], RX_ER, CRS_DV Delay from XI Clock rising 4 14 ns
RGMII INPUT TIMING
Tcyc Clock Cycle Duration TX_CLK 36 40 44 ns
Tsetup(align) TX_D[3:0], TX_CTRL Setup to TX_CLK (Align Mode) 1 2 ns
Thold(align) TX_D[3:0], TX_CTRL Hold from TX_CLK (Align Mode) 1 2 ns
RGMII OUTPUT TIMING
Tskew(align) RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled) On PHY Pins -750 750 ps
Tsetup(shift) RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode
Enabled, default)		 On PHY Pins 2 ns
Tcyc Clock Cycle Duration RX_CLK 36 40 44 ns
Duty_G Duty Cycle RX_CLK 45 50 55 %
Tr/Tf Rise / Fall Time ( 20% to 80%) CLOAD = 5pF 1.2 ns
SMI TIMING
T4.1 MDC to MDIO (Output) Delay Time 25pF load capacitance 0 40 ns
T4.2 MDIO (Input) to MDC Setup Time 10 ns
T4.3 MDIO (Input) to MDC Hold Time 10 ns
MDC Frequency 2.5 20 MHz
POWER-UP TIMING
T5.1 Supply ramp time: For all supplies (1) 0.2 8 ms
T5.2 Supply ramp delay offset: For all supplies 10 ms
T5.3 XTAL Startup / Settling: Powerup to XI good/stabilized 0.35 ms
T5.4 Oscillator stabilization time from power up 10 ms
Last Supply power up To Reset Release 10 ms
T5.5 Post power-up to SMI ready: Post Power-up wait time required before MDC preamble can be sent for register access 10 ms
T5.6 Power-up to Strap latch-in 10 ms
T5.7 CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized 10 ms
T5.8 Power-up to idle stream 10 ms
RESET TIMING (RESET_N)
T6.1 Reset Pulse Width: Miminum Reset pulse width to be able to reset 720 ns
T6.2 Reset to SMI ready: Post reset wait time required before MDC preamble can be sent for register access 1 ms
T6.3 Reset to Strap latch-in: Hardware configuration pins transition to output drivers 40 µs
T6.4 Reset to idle stream 1800 µs
TRANSMIT LATENCY TIMING
MII Rising edge TX_CLK with assertion TX_EN to SSD symbol on MD 205 233 ns
Slave RMII Rising edge XI clock with assertion TX_EN to SSD symbol on MDI 374 409 ns
Master RMII Rising edge clock with assertion TX_EN to SSD symbol on MDI 382 408 ns
RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 370 390 ns
First symbol of SGMII to SSD symbol on MDI 420 456 ns
RECEIVE LATENCY TIMING
SSD symbol on MDI to MII Rising edge of RX_CLK with assertion of RX_DV 467 491 ns
SSD symbol on MDI to Slave RMII Rising edge of XI clock with assertion of CRS_DV 527 574 ns
SSD symbol on MDI to Master RMII Rising edge of Master clock with assertion of CRS_DV 521 557 ns
SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL 484 511 ns
SSD symbol on MDI to first symbol of SGMII 708 788 ns
25 MHz OSCILLATOR REQUIREMENTS
Frequency Tolerance -100 +100 ppm
Rise / Fall Time (10%-90%) 8 ns
Jitter Tolerance (RMS) 25 ps
XI Duty Cycle in external clock mode 40 60 %
50 MHz OSCILLATOR REQUIREMENTS
Frequency 50 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Rise / Fall Time (10% - 90%) 4 ns
Duty Cycle 35 65 %
25 MHz CRYSTAL REQUIREMENTS
Frequency 25 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Equivalent Series Resistance 100 Ω
OUTPUT CLOCK TIMING (25 MHz)
Frequency (PPM) -100 100 -
Duty Cycle 40 60 %
Rise Time 5000 ps
Fall Time 5000 ps
Jitter (Short Term) 1000 ps
Frequency 25 MHz
(1) For supplies with ramp rate longer than 8ms, a RESET pulse will be required after the last supply becomes stable.
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