6.14.3.3 Watchdog Timer

The device includes one instance of the 32-bit watchdog timer: WD_TIMER2.

The watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt to the device system modules following an overflow condition. The WD_TIMER2 timer serves resets to the PRCM module (its interrupt outputs are unused).

WD_TIMER2 is located in the PD_WKUPAON power domain, and can run when the device is in lowest power state (all power domains are off except always-on (AON) and WKUP).

The watchdog timer can be accessed, loaded, and cleared by registers through the L4_WKUP interface. The watchdog timer has the 32-kHz clock for its timer clock input. WD_TIMER2 directly generates a warm reset condition on overflow.

WD_TIMER2 connects to a single target agent port on the L4_WKUP interconnect.

The main features of the watchdog timer controllers are:

• L4 slave interface support:
  • 32-bit data bus width
  • 32-/16-bit access supported
  • 8-bit access not supported
  • 11-bit address bus width
  • Burst mode not supported
  • Write nonposted mode supported

• Free-running 32-bit upward counter
• Programmable divider clock source (2ⁿ where n = [0:7])
• On-the-fly read/write register (while counting)
• Subset programming model of the GP timer
• The watchdog timer is reset either on power on or after a warm reset before it starts counting.
• Reset or interrupt actions when a timer overflow condition occurs
• The watchdog timer generates a reset or an interrupt in its hardware integration.

For more information, see section Timers of the device TRM.