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ZHCSII1F June 2016 – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

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5.5.2 Voltage And Core Clock Specifications

Table 5-3 shows the recommended OPP per voltage domain.

Table 5-3 Voltage Domains Operating Performance Points ^⁽¹⁾

DOMAIN	CONDITION	OPP_NOM			OPP_HIGH
DOMAIN	CONDITION	MIN ^⁽³⁾	NOM ^⁽²⁾	MAX ^⁽³⁾	MIN ^⁽³⁾	NOM ^⁽²⁾	MAX DC ^⁽⁴⁾	MAX ^⁽³⁾
VD_CORE (V) ^⁽⁸⁾	BOOT (Before AVS is enabled) ^⁽⁵⁾	1.11	1.15	1.2	Not Applicable
VD_CORE (V) ^⁽⁸⁾	After AVS is enabled ^⁽⁵⁾	AVS Voltage ^⁽⁶⁾ – 3.5%	AVS Voltage ^⁽⁶⁾	1.2	Not Applicable
VD_DSP (V) ^⁽⁹⁾	BOOT (Before AVS is enabled) ^⁽⁵⁾	1.02	1.06	1.16	Not Applicable
VD_DSP (V) ^⁽⁹⁾	After AVS is enabled ^⁽⁵⁾	AVS Voltage^⁽⁶⁾ – 3.5%	AVS Voltage ^⁽⁶⁾	1.2	AVS Voltage^⁽⁶⁾ – 3.5%	AVS Voltage ^⁽⁶⁾	AVS Voltage ^⁽⁶⁾ +2%	AVS Voltage^⁽⁶⁾ + 5%

The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with the ability to modify the voltage to comply with future recommendations.
In a typical implementation, the power supply should target the NOM voltage.
The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH (Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM. The power supply should be adjustable over the following ranges for each required OPP:
- OPP_NOM for DSP: 0.85 V – 1.15 V
- OPP_NOM for CORE: 0.85 V - 1.15 V
- OPP_HIGH: 1.01 V - 1.25 V
The AVS voltages will be within the above specified ranges.
The power supply must be programmed with the AVS voltages for the CORE voltage domain, either just after the ROM boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
The package routes VD_CORE (vdd) to the VD_MPU, VD_SGX, VD_CORE and VD_RTC domains on the die.
The package routes VD_DSP (vdd_dsp) to the VD_DSPEVE and VD_IVA domains on the die.

Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.

Table 5-4 Supported OPP vs Max Frequency ^⁽²⁾

DESCRIPTION	OPP_NOM	OPP_HIGH
DESCRIPTION	MAXIMUM FREQUENCY (MHz)	MAXIMUM FREQUENCY (MHz)
VD_CORE
MPU_CLK	1000	N/A
GPU_CLK	425.6	N/A
CORE_IPUx_CLK	212.8	N/A
L3_CLK	266	N/A
DDR3 / DDR3L	667 (DDR-1333)	N/A
VD_DSP
IVA_GCLK	388.3	532
DSP_CLK	600	750

N/A stands for Not Applicable.
Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-1).