ZHCSII1F June   2016  – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 ATL
      25. 4.3.25 Emulation and Debug Subsystem
      26. 4.3.26 System and Miscellaneous
        1. 4.3.26.1 Sysboot
        2. 4.3.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.26.3 System Direct Memory Access (SDMA)
        4. 4.3.26.4 Interrupt Controllers (INTC)
      27. 4.3.27 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-11 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-12 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-13 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-14 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
          3. 5.10.4.3.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-56 Timing Requirements for I2C Input Timings
          2. Table 5-57 Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)
          3. Table 5-58 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-63 Timing Requirements for UART
          2. Table 5-64 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-71 Timing Requirements for McASP1
          2. Table 5-72 Timing Requirements for McASP2
          3. Table 5-73 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
          3. 5.10.6.16.3 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-91 Timing Requirements for DCANx Receive
          2. Table 5-92 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-93 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-94 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-95 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-96 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-101 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-102 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-104 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-108 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-109 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-111 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 MLB
        21. 5.10.6.21 eMMC/SD/SDIO
          1. 5.10.6.21.1 MMC1—SD Card Interface
            1. 5.10.6.21.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.21.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.21.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.21.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.21.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.21.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.21.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.21.2 MMC2 — eMMC
            1. 5.10.6.21.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.21.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.21.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.21.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-142 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.21.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.21.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.21.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.21.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.21.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.21.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        22. 5.10.6.22 GPIO
        23. 5.10.6.23 PRU-ICSS
          1. 5.10.6.23.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.23.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-164 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-165 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.23.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-166 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.23.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-168 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.23.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-169 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-170 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-171 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.23.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.23.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-175 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-176 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.23.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.23.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-177 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-178 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-179 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.23.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-180 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-181 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-183 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.23.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-184 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-185 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.23.5 PRU-ICSS IOSETs
          6. 5.10.6.23.6 PRU-ICSS Manual Functional Mapping
        24. 5.10.6.24 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-202 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-203 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-204 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-205 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  IPU
    7. 6.7  GPU
    8. 6.8  BB2D
    9. 6.9  PRU-ICSS
    10. 6.10 Memory Subsystem
      1. 6.10.1 EMIF
      2. 6.10.2 GPMC
      3. 6.10.3 ELM
      4. 6.10.4 OCMC
    11. 6.11 Interprocessor Communication
      1. 6.11.1 MailBox
      2. 6.11.2 Spinlock
    12. 6.12 Interrupt Controller
    13. 6.13 EDMA
    14. 6.14 Peripherals
      1. 6.14.1  VIP
      2. 6.14.2  DSS
      3. 6.14.3  Timers
        1. 6.14.3.1 General-Purpose Timers
        2. 6.14.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.14.3.3 Watchdog Timer
      4. 6.14.4  I2C
      5. 6.14.5  UART
        1. 6.14.5.1 UART Features
        2. 6.14.5.2 IrDA Features
        3. 6.14.5.3 CIR Features
      6. 6.14.6  McSPI
      7. 6.14.7  QSPI
      8. 6.14.8  McASP
      9. 6.14.9  USB
      10. 6.14.10 PCIe
      11. 6.14.11 DCAN
      12. 6.14.12 GMAC_SW
      13. 6.14.13 eMMC/SD/SDIO
      14. 6.14.14 GPIO
      15. 6.14.15 ePWM
      16. 6.14.16 eCAP
      17. 6.14.17 eQEP
    15. 6.15 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 Power Regulators
        3. 7.5.2.3 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 PCIe Board Design and Layout Guidelines
        1. 7.5.5.1 PCIe Connections and Interface Compliance
          1. 7.5.5.1.1 Coupling Capacitors
          2. 7.5.5.1.2 Polarity Inversion
        2. 7.5.5.2 Non-standard PCIe connections
          1. 7.5.5.2.1 PCB Stackup Specifications
          2. 7.5.5.2.2 Routing Specifications
            1. 7.5.5.2.2.1 Impedance
            2. 7.5.5.2.2.2 Differential Coupling
            3. 7.5.5.2.2.3 Pair Length Matching
        3. 7.5.5.3 LJCB_REFN/P Connections
      6. 7.5.6 CSI2 Board Design and Routing Guidelines
        1. 7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.6.1.1 General Guidelines
          2. 7.5.6.1.2 Length Mismatch Guidelines
            1. 7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.6.1.3 Frequency-domain Specification Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR3 Board Design and Layout Guidelines
        1. 7.7.2.1  Board Designs
        2. 7.7.2.2  DDR3 EMIF
        3. 7.7.2.3  DDR3 Device Combinations
        4. 7.7.2.4  DDR3 Interface Schematic
          1. 7.7.2.4.1 32-Bit DDR3 Interface
          2. 7.7.2.4.2 16-Bit DDR3 Interface
        5. 7.7.2.5  Compatible JEDEC DDR3 Devices
        6. 7.7.2.6  PCB Stackup
        7. 7.7.2.7  Placement
        8. 7.7.2.8  DDR3 Keepout Region
        9. 7.7.2.9  Bulk Bypass Capacitors
        10. 7.7.2.10 High-Speed Bypass Capacitors
          1. 7.7.2.10.1 Return Current Bypass Capacitors
        11. 7.7.2.11 Net Classes
        12. 7.7.2.12 DDR3 Signal Termination
        13. 7.7.2.13 VREF_DDR Routing
        14. 7.7.2.14 VTT
        15. 7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.2.15.1 Four DDR3 Devices
            1. 7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.2.15.2 Two DDR3 Devices
            1. 7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.2.15.3 One DDR3 Device
            1. 7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.2.16 Data Topologies and Routing Definition
          1. 7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.2.17 Routing Specification
          1. 7.7.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.2.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • CBD|538
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.10.6.23.5 PRU-ICSS IOSETs

In Table 5-186 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS1.

Table 5-186 PRU-ICSS1 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
PRU-ICSS 1
pr1_pru1_gpi20 D13 12
pr1_pru1_gpi19 C13 12
pr1_pru1_gpi18 E13 12
pr1_pru1_gpi17 B13 12
pr1_pru1_gpi16 F11 12
pr1_pru1_gpi15 E11 12
pr1_pru1_gpi14 A13 12
pr1_pru1_gpi13 A12 12
pr1_pru1_gpi12 B12 12
pr1_pru1_gpi11 C11 12
pr1_pru1_gpi10 D11 12
pr1_pru1_gpo20 D13 13
pr1_pru1_gpo19 C13 13
pr1_pru1_gpo18 E13 13
pr1_pru1_gpo17 B13 13
pr1_pru1_gpo16 F11 13
pr1_pru1_gpo15 E11 13
pr1_pru1_gpo14 A13 13
pr1_pru1_gpo13 A12 13
pr1_pru1_gpo12 B12 13
pr1_pru1_gpo11 C11 13
pr1_pru1_gpo10 D11 13
pr1_pru1_gpi9 B11 12
pr1_pru1_gpi8 C10 12
pr1_pru1_gpi7 D10 12
pr1_pru1_gpi6 E10 12
pr1_pru1_gpi5 B10 12
pr1_pru1_gpi4 A10 12
pr1_pru1_gpi3 F10 12
pr1_pru1_gpi2 A11 12
pr1_pru1_gpi1 A8 12
pr1_pru1_gpi0 A9 12
pr1_pru1_gpo9 B11 13
pr1_pru1_gpo8 C10 13
pr1_pru1_gpo7 D10 13
pr1_pru1_gpo6 E10 13
pr1_pru1_gpo5 B10 13
pr1_pru1_gpo4 A10 13
pr1_pru1_gpo3 F10 13
pr1_pru1_gpo2 A11 13
pr1_pru1_gpo1 A8 13
pr1_pru1_gpo0 A9 13
pr1_mii1_crs D13 11
pr1_mii1_rxlink E13 11
pr1_mii1_col C13 11
pr1_mii0_col L5 11
pr1_mii0_rxlink L6 11
pr1_mii0_crs P4 11
pr1_edio_data_out7 A7 13
pr1_edio_data_out6 B9 13
pr1_edio_data_out5 C8 13
pr1_edio_data_out4 B8 13
pr1_edio_data_out3 E8 13
pr1_edio_data_out2 C7 13
pr1_edio_data_out1 B7 13
pr1_edio_data_out0 D8 13
pr1_edio_data_in7 A7 12
pr1_edio_data_in6 B9 12
pr1_edio_data_in5 C8 12
pr1_edio_data_in4 B8 12
pr1_edio_data_in3 E8 12
pr1_edio_data_in2 C7 12
pr1_edio_data_in1 B7 12
pr1_edio_data_in0 D8 12
pr1_edio_sof A11 11
pr1_edc_latch0_in A9 11
pr1_edc_sync0_out A8 11
pr1_uart0_cts_n E8 11
pr1_uart0_rts_n B8 11
pr1_uart0_txd B9 11
pr1_uart0_rxd C8 11
pr1_ecap0_ecap_capin_apwm_o A7 11
PRU-ICSS 1 MII
pr1_mii1_txd3 B10 11
pr1_mii1_txd2 E10 11
pr1_mii1_txd1 B11 11
pr1_mii1_txd0 D11 11
pr1_mii1_rxd3 A12 11
pr1_mii1_rxd2 A13 11
pr1_mii1_rxd1 E11 11
pr1_mii1_rxd0 F11 11
pr1_mii1_rxdv B12 11
pr1_mii1_txen A10 11
pr1_mii1_rxer B13 11
pr1_mii_mr1_clk C11 11
pr1_mii_mt1_clk F10 11
pr1_mii0_txd3 P2 11
pr1_mii0_txd2 N1 11
pr1_mii0_txd1 N3 11
pr1_mii0_txd0 N4 11
pr1_mii0_rxd3 T4 11
pr1_mii0_rxd2 T5 11
pr1_mii0_rxd1 R2 11
pr1_mii0_rxd0 R1 11
pr1_mii0_rxdv N5 11
pr1_mii0_txen P1 11
pr1_mii0_rxer P3 11
pr1_mii_mt0_clk N2 11
pr1_mii_mr0_clk N6 11
pr1_mdio_mdclk D10 11
pr1_mdio_data C10 11

In Table 5-187, Table 5-188 and Table 5-189 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS2.

Table 5-187 PRU-ICSS2 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
PRU-ICSS 2
pr2_pru1_gpi16 N4 12 E16 12
pr2_pru1_gpi15 N3 12 E17 12
pr2_pru1_gpi14 P1 12 A19 12
pr2_pru1_gpi13 N1 12 B18 12
pr2_pru1_gpi12 P2 12 B16 12
pr2_pru1_gpi11 N2 12 B17 12
pr2_pru1_gpi10 R1 12 A18 12
pr2_pru1_gpi9 R2 12 B14 12
pr2_pru1_gpi8 P3 12 D14 12
pr2_pru1_gpi7 P4 12 C16 12
pr2_pru1_gpi6 T5 12 J24 12
pr2_pru1_gpi5 T4 12 J25 12
pr2_pru1_gpi4 N6 12 AC4 12
pr2_pru1_gpi3 N5 12 AA5 12
pr2_pru1_gpi2 P5 12 U6 12
pr2_pru1_gpi1 L6 12 AC3 12
pr2_pru1_gpi0 L5 12 D23 12
pr2_pru1_gpo16 N4 13 E16 13
pr2_pru1_gpo15 N3 13 E17 13
pr2_pru1_gpo14 P1 13 A19 13
pr2_pru1_gpo13 N1 13 B18 13
pr2_pru1_gpo12 P2 13 B16 13
pr2_pru1_gpo11 N2 13 B17 13
pr2_pru1_gpo10 R1 13 A18 13
pr2_pru1_gpo9 R2 13 B14 13
pr2_pru1_gpo8 P3 13 D14 13
pr2_pru1_gpo7 P4 13 C16 13
pr2_pru1_gpo6 T5 13 J24 13
pr2_pru1_gpo5 T4 13 J25 13
pr2_pru1_gpo4 N6 13 AC4 13
pr2_pru1_gpo3 N5 13 AA5 13
pr2_pru1_gpo2 P5 13 U6 13
pr2_pru1_gpo1 L6 13 AC3 13
pr2_pru1_gpo0 L5 13 D23 13
pr2_pru0_gpi20 F16 12
pr2_pru0_gpi19 D19 12
pr2_pru0_gpi18 E19 12
pr2_pru0_gpi17 B21 12
pr2_pru0_gpi16 A21 12
pr2_pru0_gpi15 B23 12
pr2_pru0_gpi14 B22 12
pr2_pru0_gpi13 A23 12
pr2_pru0_gpi12 A22 12
pr2_pru0_gpi11 AB1 12
pr2_pru0_gpi10 AA4 12
pr2_pru0_gpi9 AA1 12
pr2_pru0_gpi8 Y3 12
pr2_pru0_gpi7 W2 12
pr2_pru0_gpi6 AA3 12
pr2_pru0_gpi5 AA2 12
pr2_pru0_gpi4 Y4 12
pr2_pru0_gpi3 Y1 12
pr2_pru0_gpi2 Y2 12
pr2_pru0_gpi1 Y6 12
pr2_pru0_gpi0 Y5 12
pr2_pru0_gpo20 F16 13
pr2_pru0_gpo19 D19 13
pr2_pru0_gpo18 E19 13
pr2_pru0_gpo17 B21 13
pr2_pru0_gpo16 A21 13
pr2_pru0_gpo15 B23 13
pr2_pru0_gpo14 B22 13
pr2_pru0_gpo13 A23 13
pr2_pru0_gpo12 A22 13
pr2_pru0_gpo11 AB1 13
pr2_pru0_gpo10 AA4 13
pr2_pru0_gpo9 AA1 13
pr2_pru0_gpo8 Y3 13
pr2_pru0_gpo7 W2 13
pr2_pru0_gpo6 AA3 13
pr2_pru0_gpo5 AA2 13
pr2_pru0_gpo4 Y4 13
pr2_pru0_gpo3 Y1 13
pr2_pru0_gpo2 Y2 13
pr2_pru0_gpo1 Y6 13
pr2_pru0_gpo0 Y5 13
pr2_mii1_crs J24 11
pr2_mii1_rxlink B23 11
pr2_mii0_crs A22 11
pr2_mii0_rxlink B21 11
pr2_mii0_col A23 11
pr2_mii1_col J25 11
PRU-ICSS 2 MII
pr2_mii1_txd3 Y2 11
pr2_mii1_txd2 Y1 11
pr2_mii1_txd1 Y4 11
pr2_mii1_txd0 AA2 11
pr2_mii1_rxd3 Y3 11
pr2_mii1_rxd2 AA1 11
pr2_mii1_rxd1 AA4 11
pr2_mii1_rxd0 AB1 11
pr2_mii_mr1_clk AA3 11
pr2_mii1_rxer B22 11
pr2_mii_mt1_clk Y5 11
pr2_mii1_rxdv W2 11
pr2_mii1_txen Y6 11
pr2_mii0_txd3 B17 11
pr2_mii0_txd2 B16 11
pr2_mii0_txd1 B18 11
pr2_mii0_txd0 A19 11
pr2_mii0_rxd3 F16 11
pr2_mii0_rxd2 E19 11
pr2_mii0_rxd1 D19 11
pr2_mii0_rxd0 A21 11
pr2_mii_mr0_clk E17 11
pr2_mii0_rxer D14 11
pr2_mii_mt0_clk B14 11
pr2_mii0_rxdv E16 11
pr2_mii0_txen A18 11
pr2_mdio_mdclk C16 11 AA5 11
pr2_mdio_data C17 11 AC4 11

Table 5-188 PRU-ICSS2 IOSETs (EnDAT)(1)

SIGNALS IOSET3 IOSET4
BALL MUX BALL MUX
PRU-ICSS 2 EnDAT
pr2_pru1_endat0_clk L5 13 D23 13
pr2_pru1_endat0_out L6 13 AC3 13
pr2_pru1_endat0_out_en P5 13 U6 13
pr2_pru1_endat1_clk N5 13 AA5 13
pr2_pru1_endat1_out N6 13 AC4 13
pr2_pru1_endat1_out_en T4 13 J25 13
pr2_pru1_endat2_clk T5 13 J24 13
pr2_pru1_endat2_out P4 13 C16 13
pr2_pru1_endat2_out_en P3 13 D14 13
pr2_pru1_endat0_in R2 12 B14 12
pr2_pru1_endat1_in R1 12 A18 12
pr2_pru1_endat2_in N2 12 B17 12
  1. These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the PRU-ICSS internal wrapper multiplexing.

Table 5-189 PRU-ICSS2 IOSETs (Sigma Delta)(1)

SIGNALS IOSET4
BALL MUX
PRU-ICSS 2 SD
pr2_pru0_sd0_clk Y5 12
pr2_pru0_sd0_d Y6 12
pr2_pru0_sd1_clk Y2 12
pr2_pru0_sd1_d Y1 12
pr2_pru0_sd2_clk Y4 12
pr2_pru0_sd2_d AA2 12
pr2_pru0_sd3_clk AA3 12
pr2_pru0_sd3_d W2 12
pr2_pru0_sd4_clk Y3 12
pr2_pru0_sd4_d AA1 12
pr2_pru0_sd5_clk AA4 12
pr2_pru0_sd5_d AB1 12
pr2_pru0_sd6_clk A22 12
pr2_pru0_sd6_d A23 12
pr2_pru0_sd7_clk B22 12
pr2_pru0_sd7_d B23 12
pr2_pru0_sd8_clk A21 12
pr2_pru0_sd8_d B21 12
  1. These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the PRU-ICSS internal wrapper multiplexing.
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