ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
Table 7-106 and Table 7-107 present Timing requirements and Switching characteristics for MMC1 - SDR25 in receiver and transmitter mode (see Figure 7-68 and Figure 7-69).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SDR253 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 5.3 | ns | ||
SDR254 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | 1.6 | ns | ||
SDR257 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 5.3 | ns | ||
SDR258 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | Pad Loopback Clock | 1.6 | ns | |
Internal Loopback Clock | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR251 | fop(clk) | Operating frequency, mmc1_clk | 48 | MHz | |
SDR252H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5*P-0.185 (1) | ns | |
SDR252L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5*P-0.185 (1) | ns | |
SDR255 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -8.8 | 6.6 | ns |
SDR256 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -8.8 | 6.6 | ns |