ZHCSJ33F December   2015  – May 2019 DRA745 , DRA746 , DRA750 , DRA756

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 SATA
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM) Interface
      23. 4.4.23 Audio Tracking Logic (ATL)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.25.3 Real Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
      26. 4.4.26 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  ILVDS18 Buffers DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
      3. 7.18.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
      1. Table 7-69 Timing Requirements for DCANx Receive
      2. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-71 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-72 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-73 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-74 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-79 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-80 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-81 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-82 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-86 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-87 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-88 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-89 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 Media Local Bus (MLB) interface
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1—SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 — eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.24.3 MMC3 and MMC4—SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 Audio Tracking Logic (ATL)
      1. 7.26.1 ATL Electrical Data/Timing
        1. Table 7-145 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-146 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-147 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-148 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-149 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商标
    7. 9.7 静电放电警告
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABC|760
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.4.20 General-Purpose Interface (GPIO)

NOTE

For more information, see the General-Purpose Interface section of the device TRM.

Table 4-23 GPIOs Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
GPIO 1
gpio1_0 General-Purpose Input I AD17
gpio1_1 General-Purpose Input I AC17
gpio1_2 General-Purpose Input I AB16
gpio1_3 General-Purpose Input I AC16
gpio1_4 General-Purpose Input/Output IO D15
gpio1_5 General-Purpose Input/Output IO A17
gpio1_6 General-Purpose Input/Output IO M6
gpio1_7 General-Purpose Input/Output IO M2
gpio1_8 General-Purpose Input/Output IO L5
gpio1_9 General-Purpose Input/Output IO M1
gpio1_10 General-Purpose Input/Output IO L6
gpio1_11 General-Purpose Input/Output IO L4
gpio1_12 General-Purpose Input/Output IO L3
gpio1_13 General-Purpose Input/Output IO L2
gpio1_14 General-Purpose Input/Output IO G20
gpio1_15 General-Purpose Input/Output IO G19
gpio1_16 General-Purpose Input/Output IO D27
gpio1_17 General-Purpose Input/Output IO C28
gpio1_18 General-Purpose Input/Output IO H1
gpio1_19 General-Purpose Input/Output IO J3
gpio1_20 General-Purpose Input/Output IO H2
gpio1_21 General-Purpose Input/Output IO H3
gpio1_22 General-Purpose Input/Output IO AC8
gpio1_23 General-Purpose Input/Output IO AD6
gpio1_24 General-Purpose Input/Output IO AB8
gpio1_25 General-Purpose Input/Output IO AB5
gpio1_26 General-Purpose Input/Output IO P6
gpio1_27 General-Purpose Input/Output IO R9
gpio1_28 General-Purpose Input/Output IO R5
gpio1_29 General-Purpose Input/Output IO P5
gpio1_30 General-Purpose Input/Output IO N7
gpio1_31 General-Purpose Input/Output IO R4
GPIO 2
gpio2_0 General-Purpose Input/Output IO N9
gpio2_1 General-Purpose Input/Output IO P9
gpio2_2 General-Purpose Input/Output IO P4
gpio2_3 General-Purpose Input/Output IO R3
gpio2_4 General-Purpose Input/Output IO T2
gpio2_5 General-Purpose Input/Output IO U2
gpio2_6 General-Purpose Input/Output IO U1
gpio2_7 General-Purpose Input/Output IO P3
gpio2_8 General-Purpose Input/Output IO R2
gpio2_9 General-Purpose Input/Output IO K7
gpio2_10 General-Purpose Input/Output IO M7
gpio2_11 General-Purpose Input/Output IO J5
gpio2_12 General-Purpose Input/Output IO K6
gpio2_13 General-Purpose Input/Output IO J7
gpio2_14 General-Purpose Input/Output IO J4
gpio2_15 General-Purpose Input/Output IO J6
gpio2_16 General-Purpose Input/Output IO H4
gpio2_17 General-Purpose Input/Output IO H5
gpio2_18 General-Purpose Input/Output IO H6
gpio2_19 General-Purpose Input/Output IO T1
gpio2_20 General-Purpose Input/Output IO P2
gpio2_21 General-Purpose Input/Output IO P1
gpio2_22 General-Purpose Input/Output IO P7
gpio2_23 General-Purpose Input/Output IO N1
gpio2_24 General-Purpose Input/Output IO M5
gpio2_25 General-Purpose Input/Output IO M3
gpio2_26 General-Purpose Input/Output IO N6
gpio2_27 General-Purpose Input/Output IO M4
gpio2_28 General-Purpose Input/Output IO N2
gpio2_29 General-Purpose Input/Output IO B17
gpio2_30 General-Purpose Input/Output IO AG8
gpio2_31 General-Purpose Input/Output IO AH7
GPIO 3
gpio3_0 General-Purpose Input/Output IO AD9
gpio3_1 General-Purpose Input/Output IO AF9
gpio3_2 General-Purpose Input/Output IO AE9
gpio3_3 General-Purpose Input/Output IO AF8
gpio3_4 General-Purpose Input/Output IO AE8
gpio3_5 General-Purpose Input/Output IO AD8
gpio3_6 General-Purpose Input/Output IO AG7
gpio3_7 General-Purpose Input/Output IO AH6
gpio3_8 General-Purpose Input/Output IO AH3
gpio3_9 General-Purpose Input/Output IO AH5
gpio3_10 General-Purpose Input/Output IO AG6
gpio3_11 General-Purpose Input/Output IO AH4
gpio3_12 General-Purpose Input/Output IO AG4
gpio3_13 General-Purpose Input/Output IO AG2
gpio3_14 General-Purpose Input/Output IO AG3
gpio3_15 General-Purpose Input/Output IO AG5
gpio3_16 General-Purpose Input/Output IO AF2
gpio3_17 General-Purpose Input/Output IO AF6
gpio3_18 General-Purpose Input/Output IO AF3
gpio3_19 General-Purpose Input/Output IO AF4
gpio3_20 General-Purpose Input/Output IO AF1
gpio3_21 General-Purpose Input/Output IO AE3
gpio3_22 General-Purpose Input/Output IO AE5
gpio3_23 General-Purpose Input/Output IO AE1
gpio3_24 General-Purpose Input/Output IO AE2
gpio3_25 General-Purpose Input/Output IO AE6
gpio3_26 General-Purpose Input/Output IO AD2
gpio3_27 General-Purpose Input/Output IO AD3
gpio3_28 General-Purpose Input/Output IO E1
gpio3_29 General-Purpose Input/Output IO G2
gpio3_30 General-Purpose Input/Output IO H7
gpio3_31 General-Purpose Input/Output IO G1
GPIO 4
gpio4_0 General-Purpose Input/Output IO G6
gpio4_1 General-Purpose Input/Output IO F2
gpio4_2 General-Purpose Input/Output IO F3
gpio4_3 General-Purpose Input/Output IO D1
gpio4_4 General-Purpose Input/Output IO E2
gpio4_5 General-Purpose Input/Output IO D2
gpio4_6 General-Purpose Input/Output IO F4
gpio4_7 General-Purpose Input/Output IO C1
gpio4_8 General-Purpose Input/Output IO E4
gpio4_9 General-Purpose Input/Output IO F5
gpio4_10 General-Purpose Input/Output IO E6
gpio4_11 General-Purpose Input/Output IO D3
gpio4_12 General-Purpose Input/Output IO F6
gpio4_13 General-Purpose Input/Output IO D5
gpio4_14 General-Purpose Input/Output IO C2
gpio4_15 General-Purpose Input/Output IO C3
gpio4_16 General-Purpose Input/Output IO C4
gpio4_17 General-Purpose Input/Output IO A12
gpio4_18 General-Purpose Input/Output IO E14
gpio4_19 General-Purpose Input/Output IO D11
gpio4_20 General-Purpose Input/Output IO B10
gpio4_21 General-Purpose Input/Output IO B11
gpio4_22 General-Purpose Input/Output IO C11
gpio4_23 General-Purpose Input/Output IO E11
gpio4_24 General-Purpose Input/Output IO B2
gpio4_25 General-Purpose Input/Output IO D6
gpio4_26 General-Purpose Input/Output IO C5
gpio4_27 General-Purpose Input/Output IO A3
gpio4_28 General-Purpose Input/Output IO B3
gpio4_29 General-Purpose Input/Output IO B4
gpio4_30 General-Purpose Input/Output IO B5
gpio4_31 General-Purpose Input/Output IO A4
GPIO 5
gpio5_0 General-Purpose Input/Output IO B14
gpio5_1 General-Purpose Input/Output IO J14
gpio5_2 General-Purpose Input/Output IO G12
gpio5_3 General-Purpose Input/Output IO F12
gpio5_4 General-Purpose Input/Output IO G13
gpio5_5 General-Purpose Input/Output IO J11
gpio5_6 General-Purpose Input/Output IO E12
gpio5_7 General-Purpose Input/Output IO F13
gpio5_8 General-Purpose Input/Output IO C12
gpio5_9 General-Purpose Input/Output IO D12
gpio5_10 General-Purpose Input/Output IO B12
gpio5_11 General-Purpose Input/Output IO A11
gpio5_12 General-Purpose Input/Output IO B13
gpio5_13 General-Purpose Input/Output IO B18
gpio5_14 General-Purpose Input/Output IO F15
gpio5_15 General-Purpose Input/Output IO V1
gpio5_16 General-Purpose Input/Output IO U4
gpio5_17 General-Purpose Input/Output IO U3
gpio5_18 General-Purpose Input/Output IO V2
gpio5_19 General-Purpose Input/Output IO Y1
gpio5_20 General-Purpose Input/Output IO W9
gpio5_21 General-Purpose Input/Output IO V9
gpio5_22 General-Purpose Input/Output IO V7
gpio5_23 General-Purpose Input/Output IO U7
gpio5_24 General-Purpose Input/Output IO V6
gpio5_25 General-Purpose Input/Output IO U6
gpio5_26 General-Purpose Input/Output IO U5
gpio5_27 General-Purpose Input/Output IO V5
gpio5_28 General-Purpose Input/Output IO V4
gpio5_29 General-Purpose Input/Output IO V3
gpio5_30 General-Purpose Input/Output IO Y2
gpio5_31 General-Purpose Input/Output IO W2
GPIO 6
gpio6_4 General-Purpose Input/Output IO A13
gpio6_5 General-Purpose Input/Output IO G14
gpio6_6 General-Purpose Input/Output IO F14
gpio6_7 General-Purpose Input/Output IO B16
gpio6_8 General-Purpose Input/Output IO C15
gpio6_9 General-Purpose Input/Output IO A16
gpio6_10 General-Purpose Input/Output IO AC5
gpio6_11 General-Purpose Input/Output IO AB4
gpio6_12 General-Purpose Input/Output IO AB10
gpio6_13 General-Purpose Input/Output IO AC10
gpio6_14 General-Purpose Input/Output IO E21
gpio6_15 General-Purpose Input/Output IO F20
gpio6_16 General-Purpose Input/Output IO F21
gpio6_17 General-Purpose Input/Output IO D18
gpio6_18 General-Purpose Input/Output IO E17
gpio6_19 General-Purpose Input/Output IO B26
gpio6_20 General-Purpose Input/Output IO C23
gpio6_21 General-Purpose Input/Output IO W6
gpio6_22 General-Purpose Input/Output IO Y6
gpio6_23 General-Purpose Input/Output IO AA6
gpio6_24 General-Purpose Input/Output IO Y4
gpio6_25 General-Purpose Input/Output IO AA5
gpio6_26 General-Purpose Input/Output IO Y3
gpio6_27 General-Purpose Input/Output IO W7
gpio6_28 General-Purpose Input/Output IO Y9
gpio6_29 General-Purpose Input/Output IO AD4
gpio6_30 General-Purpose Input/Output IO AC4
gpio6_31 General-Purpose Input/Output IO AC7
GPIO 7
gpio7_0 General-Purpose Input/Output IO AC6
gpio7_1 General-Purpose Input/Output IO AC9
gpio7_2 General-Purpose Input/Output IO AC3
gpio7_3 General-Purpose Input/Output IO R6
gpio7_4 General-Purpose Input/Output IO T9
gpio7_5 General-Purpose Input/Output IO T6
gpio7_6 General-Purpose Input/Output IO T7
gpio7_7 General-Purpose Input/Output IO A25
gpio7_8 General-Purpose Input/Output IO F16
gpio7_9 General-Purpose Input/Output IO B25
gpio7_10 General-Purpose Input/Output IO A24
gpio7_11 General-Purpose Input/Output IO A22
gpio7_12 General-Purpose Input/Output IO B21
gpio7_13 General-Purpose Input/Output IO B20
gpio7_14 General-Purpose Input/Output IO A26
gpio7_15 General-Purpose Input/Output IO B22
gpio7_16 General-Purpose Input/Output IO G17
gpio7_17 General-Purpose Input/Output IO B24
gpio7_18 General-Purpose Input/Output IO L1
gpio7_19 General-Purpose Input/Output IO K2
gpio7_22 General-Purpose Input/Output IO B27
gpio7_23 General-Purpose Input/Output IO C26
gpio7_24 General-Purpose Input/Output IO E25
gpio7_25 General-Purpose Input/Output IO C27
gpio7_26 General-Purpose Input/Output IO D28
gpio7_27 General-Purpose Input/Output IO D26
gpio7_28 General-Purpose Input/Output IO J1
gpio7_29 General-Purpose Input/Output IO J2
gpio7_30 General-Purpose Input/Output IO D14
gpio7_31 General-Purpose Input/Output IO C14
GPIO 8
gpio8_0 General-Purpose Input/Output IO F11
gpio8_1 General-Purpose Input/Output IO G10
gpio8_2 General-Purpose Input/Output IO F10
gpio8_3 General-Purpose Input/Output IO G11
gpio8_4 General-Purpose Input/Output IO E9
gpio8_5 General-Purpose Input/Output IO F9
gpio8_6 General-Purpose Input/Output IO F8
gpio8_7 General-Purpose Input/Output IO E7
gpio8_8 General-Purpose Input/Output IO E8
gpio8_9 General-Purpose Input/Output IO D9
gpio8_10 General-Purpose Input/Output IO D7
gpio8_11 General-Purpose Input/Output IO D8
gpio8_12 General-Purpose Input/Output IO A5
gpio8_13 General-Purpose Input/Output IO C6
gpio8_14 General-Purpose Input/Output IO C8
gpio8_15 General-Purpose Input/Output IO C7
gpio8_16 General-Purpose Input/Output IO B7
gpio8_17 General-Purpose Input/Output IO B8
gpio8_18 General-Purpose Input/Output IO A7
gpio8_19 General-Purpose Input/Output IO A8
gpio8_20 General-Purpose Input/Output IO C9
gpio8_21 General-Purpose Input/Output IO A9
gpio8_22 General-Purpose Input/Output IO B9
gpio8_23 General-Purpose Input/Output IO A10
gpio8_27 General-Purpose Input I D23
gpio8_28 General-Purpose Input/Output IO F19
gpio8_29 General-Purpose Input/Output IO E18
gpio8_30(1) General-Purpose Input/Output IO G21
gpio8_31(1) General-Purpose Input/Output IO D24
  1. gpio8_30 is multiplexed with EMU0 and gpio8_31 is multiplexed with EMU1. These pins will be sampled at reset release by the test and emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |