6.10.5.1 General-Purpose Timers
The device has eight GP timers: TIMER1 through TIMER8.
- TIMER1 (1-ms tick) includes a specific function to generate accurate tick interrupts to the operating system and it belongs to the PD_WKUPAON domain.
- TIMER2 through TIMER8 belong to the PD_COREAON module.
Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. Select the clock source at the power, reset, and clock management (PRCM) module level.
Each timer provides an interrupt through the device IRQ_CROSSBAR.
The following are the main features of the GP timer controllers:
- Level 4 (L4) slave interface support:
- 32-bit data bus width
- 32-/16-bit access supported
- 8-bit access not supported
- 10-bit address bus width
- Burst mode not supported
- Write nonposted transaction mode supported
- Interrupts generated on overflow, compare, and capture
- Free-running 32-bit upward counter
- Compare and capture modes
- Autoreload mode
- Start and stop mode
- Programmable divider clock source (2n, where n = [0:8])
- Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
- Dedicated GP output signal for using the TIMERi_GPO_CFG signal
- On-the-fly read/write register (while counting)
- 1-ms tick with 32.768-Hz functional clock generated (only TIMER1)
For more information, see section General-Purpose Timers in chapter Timers of the device TRM.