6.10.8 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules are able to work as both master and slave and support the following chip selects:
- MCSPI1: spi1_cs[0], spi1_cs[1], spi1_cs[2], spi1_cs[3]
- MCSPI2: spi2_cs[0], spi2_cs[1]
- MCSPI3: spi3_cs[0], spi3_cs[1]
- MCSPI4: spi4_cs[0]
The McSPI modules include the following main features:
- Serial clock with programmable frequency, polarity, and phase for each channel
- Wide selection of SPI word lengths, ranging from 4 to 32 bits
- Up to four master channels, or single channel in slave mode
- Master multichannel mode:
- Full duplex/half duplex
- Transmit-only/receive-only/transmit-and-receive modes
- Flexible input/output (I/O) port controls per channel
- Programmable clock granularity
- SPI configuration per channel. This means, clock definition, polarity enabling and word width
- Single interrupt line for multiple interrupt source events
- Power management through wake-up capabilities
- Enable the addition of a programmable start-bit for SPI transfer per channel (start-bit mode)
- Supports start-bit write command
- Supports start-bit pause and break sequence
- Programmable timing control between chip select and external clock generation
- Built-in FIFO available for a single channel
For more information, see section Multichannel Serial Peripheral Interface in chapter Serial Communication Interfaces of the device TRM.