7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):

• The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
• The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must be approximately equal to the signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D).
• The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be approximately equal to the signal propagation delay of the control and data signals between the QSPI device and the SoC device (E to F, or F to E).
• The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-19.
• Propagation delays and matching:
  • A to C = C to D = E to F
  • Matching skew: < 60pS
  • A to B < 450pS
  • B to C = as small as possible (<60pS)

Figure 7-19 QSPI Interface High Level Schematic Mode 0 (POL=0, PHA=0)