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ZHCSII2E August 2016 – May 2019 DRA790 , DRA791 , DRA793 , DRA797

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5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing

CAUTION

The I/O Timings provided in this section are valid only for some GPMC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

Table 5-51 and Table 5-52 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-29, Figure 5-30, Figure 5-31, Figure 5-32, Figure 5-33 and Figure 5-34).

Table 5-51 GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
FA5	t_acc(DAT)	Data Maximum Access Time (GPMC_FCLK cycles)		H ^⁽¹⁾	cycles
FA20	t_{acc1-pgmode(DAT)}	Page Mode Successive Data Maximum Access Time (GPMC_FCLK cycles)		P ^⁽²⁾	cycles
FA21	t_{acc2-pgmode(DAT)}	Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)		H ^⁽¹⁾	cycles
-	t_su(DV-OEH)	Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high	1.9		ns
-	t_h(OEH-DV)	Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high	1		ns

H = Access Time × (TimeParaGranularity + 1)
P = PageBurstAccessTime × (TimeParaGranularity + 1)

Table 5-52 GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
-	t_r(DO)	Rising time, gpmc_ad[15:0] output data	0.447	4.067	ns
-	t_f(DO)	Fallling time, gpmc_ad[15:0] output data	0.43	4.463	ns
FA0	t_w(nBEV)	Pulse duration, gpmc_ben[1:0] valid time		N ^⁽¹⁾	ns
FA1	t_w(nCSV)	Pulse duration, gpmc_cs[7:0] low		A ^⁽²⁾	ns
FA3	t_{d(nCSV-nADVIV)}	Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid	B - 2 ^⁽³⁾	B + 4 ^⁽³⁾	ns
FA4	t_{d(nCSV-nOEIV)}	Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)	C - 2 ^⁽⁴⁾	C + 4 ^⁽⁴⁾	ns
FA9	t_d(AV-nCSV)	Delay time, address bus valid to gpmc_cs[7:0] valid	J - 2 ^⁽⁵⁾	J + 4 ^⁽⁵⁾	ns
FA10	t_d(nBEV-nCSV)	Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid	J - 2 ^⁽⁵⁾	J + 4 ^⁽⁵⁾	ns
FA12	t_{d(nCSV-nADVV)}	Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid	K - 2 ^⁽⁶⁾	K + 4 ^⁽⁶⁾	ns
FA13	t_d(nCSV-nOEV)	Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid	L - 2 ^⁽⁷⁾	L + 4 ^⁽⁷⁾	ns
FA16	t_w(AIV)	Pulse duration, address invalid between 2 successive R/W accesses	G ^⁽⁸⁾		ns
FA18	t_{d(nCSV-nOEIV)}	Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)	I - 2 ^⁽⁹⁾	I + 4 ^⁽⁹⁾	ns
FA20	t_w(AV)	Pulse duration, address valid : 2nd, 3rd and 4th accesses	D ^⁽¹⁰⁾		ns
FA25	t_d(nCSV-nWEV)	Delay time, gpmc_cs[7:0] valid to gpmc_wen valid	E - 2 ^⁽¹¹⁾	E + 4 ^⁽¹¹⁾	ns
FA27	t_{d(nCSV-nWEIV)}	Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid	F - 2 ^⁽¹²⁾	F + 4 ^⁽¹²⁾	ns
FA28	t_d(nWEV-DV)	Delay time, gpmc_ wen valid to data bus valid		2	ns
FA29	t_d(DV-nCSV)	Delay time, data bus valid to gpmc_cs[7:0] valid	J - 2 ^⁽⁵⁾	J + 4 ^⁽⁵⁾	ns
FA37	t_d(nOEV-AIV)	Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus phase end		2	ns

For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK
K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
G = Cycle2CycleDelay × GPMC_FCLK × (TimeParaGranularity +1)
I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK
E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK
F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_07.gif

Figure 5-29 GPMC / NOR Flash - Asynchronous Read - Single Word Timing^{⁽¹⁾⁽²⁾⁽³⁾}

In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_08.gif

Figure 5-30 GPMC / NOR Flash - Asynchronous Read - 32-bit Timing^{⁽¹⁾⁽²⁾⁽³⁾}

In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_09.gif

Figure 5-31 GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing^{⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾}

In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime register bits field.
FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_10.gif

Figure 5-32 GPMC / NOR Flash - Asynchronous Write - Single Word Timing^⁽¹⁾

In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_11.gif

Figure 5-33 GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing^{⁽¹⁾⁽²⁾⁽³⁾}

In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock edge. FA5 value should be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.

DRA790 DRA791 DRA793 DRA797 SPRS906_TIMING_GPMC_12.gif

Figure 5-34 GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing^⁽¹⁾

In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal direction on the GPMC data bus.