6.5 IPU

The device instantiates two dual Cortex-M4 image processor unit (IPU) subsystems

Each IPU subsystem contains two Arm Cortex-M4 processors (IPUx_C0 and IPUx_C1) that share a common level 1 (L1) cache (called unicache [IPUx_UNICACHE]). The two Cortex-M4 cores are completely homogeneous to one another. Any task possible using one Cortex-M4 core is also possible using the other Cortex-M4 core. It is software responsibility to distribute the various tasks between each Cortex-M4 core for optimal performance.

The integrated interrupt handling of the IPUx subsystem allows it to function as an efficient control unit.

Each IPU subsystem integrates the following:

• Two Arm Cortex-M4 microprocessors (IPUx_C0 and IPUx_C1):
  • Armv7-M and Thumb®-2 instruction set architecture (ISA)
  • Armv6 SIMD and digital signal processor (DSP) extensions
  • Single-cycle MAC
  • Integrated nested vector interrupt controller (NVIC) (also called IPUx_Cx_INTC, where x = 0, 1)
  • Integrated bus matrix
  • Registers:
    • Thirteen general-purpose 32-bit registers
    • Link register (LR)
    • Program counter (PC)
    • Program status register, xPSR
    • Two banked SP registers
  • Integrated power management
  • Extensive debug capabilities
• Unicache interface:
  • Instruction and data interface
  • Supports paralleled accesses
• Level 2 (L2) master interface (MIF) splitter for access to memory or configuration port
• Configuration port: Used for unicache maintenance and unicache memory management unit (IPUx_UNICACHE_MMU) configuration
• Unicache:
  • 32 KiB divided into 16 banks
  • 4-way
  • Cache configuration lock/freeze/preload
  • Internal MMU:
    • 16-entry region-based address translation
    • Read/write control and access type control
    • Execute Never (XN) MMU protection policy
    • Little-endian format
• Subsystem counter timer module (IPUx_UNICACHE_SCTM, or just SCTM)
• On-chip ROM (IPUx_ROM) and banked RAM (IPUx_RAM) memory
• Emulation/debug: Emulation feature embedded in Cortex-M4
• L2 MMU (IPUx_MMU): 32 entries with table walking logic
• Wake-up generator (IPUx_WUGEN): Generates wake-up request from external interrupts
• Power management:
  • Local power-management control: Configurable through the IPUx_WUGEN registers.
  • Three sleep modes supported, controlled by the local power-management module.
  • IPUx is clock-gated in all sleep modes.
  • IPUx_Cx_INTC interrupt interface stays awake.

For more information, see chapter Dual Cortex-M4 IPU Subsystem of the device TRM.