6.7.4 OCMC

There is one on-chip memory controller (OCMC) in the device.

The OCM Controller supports the following features:

• L3_MAIN data interface:
  • Used for maximum throughput performance
  • 128-bit data bus width
  • Burst supported
• L4 interface (OCMC_RAM only):
  • Used for access to configuration registers
  • 32-bit data bus width
  • Only single accesses supported
  • The L4 associated OCMC clock is two times lower than the L3 associated OCMC clock
• Error correction and detection:
  • Single error correction and dual error detection
  • 9-bit Hamming error correction code (ECC) calculated on 128-bit data word which is concatenated with memory address bits
  • Hamming distance of 4
  • Enable/Disable mode control through a dedicated register
  • Single bit error correction on a read transaction
  • Exclusion of repeated addresses from correctable error address trace history
  • ECC valid for all write transactions to an enabled region
  • Sub-128-bit writes supported via read modify write
• ECC Error Status Reporting:
  • Trace history buffer (FIFO) with depth of 4 for corrected error address
  • Trace history buffer with depth of 4 for non correctable error address and also including double error detection
  • Interrupt generation for correctable and uncorrectable detected errors
• ECC Diagnostics Configuration:
  • Counters for single error correction (SEC), double error detection (DED) and address error events (AEE)
  • Programmable threshold registers for exeptions associated with SEC, DED and AEE counters
  • Register control for enabling and disabling of diagnostics
  • Configuration registers and ECC status accessible through L4 interconnect
• Circular buffer for sliced based VIP frame transfers:
  • Up to 12 programmable circular buffers mapped with unique virtual frame addresses
  • On the fly (with no additional latency) address translation from virtual to OCMC circular buffer memory space
  • Virtual frame size up to 8 MiB and circular buffer size up to 1 MiB
  • Error handling and reporting of illegal CBUF addressing
  • Underflow and Overflow status reporting and error handling
  • Last access read/write address history
• Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events

The OCM controller does not have a memory protection logic and does not support endianism conversion.

For more information, see section On-Chip Memory (OCM) in chapter Memory Subsystem of the device TRM.