米6体育平台手机版

ZHCSKS2E april 2020 – june 2023 DRA821U , DRA821U-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

NO.⁽¹⁾	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
O1	t_c(CLK)	Cycle time, CLK	1.8V	19		ns
O1	t_c(CLK)	Cycle time, CLK	3.3V	19		ns
O2	t_w(CLKL)	Pulse duration, CLK low		-0.3+0.475*P ⁽²⁾		ns
O3	t_w(CLKH)	Pulse duration, CLK high		-0.3+0.475*P ⁽²⁾		ns
O4	t_d(CLK-CSn)	Delay time, CSn[3:0] active edge to CLK rising edge	1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX	-7-0.475 * P – 0.975 * N * R ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	0.525 * P + 1.025 * M * R + 1 ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O4	t_d(CLK-CSn)	Delay time, CSn[3:0] active edge to CLK rising edge	3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX	-7-0.475 * P – 0.975 * N * R ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	0.525 * P + 1.025 * M * R + 1 ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX	-7+0.475 * P + 0.975 * N * R ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	0.525 * P + 1.025 * N * R + 1 ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX	-7+0.475 * P + 0.975 * N * R ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	0.525 * P + 1.025 * N * R + 1 ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition	1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX	-7.7	-1.56	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition	3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX	-7.7	-1.56	ns

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time

(3) P = SCLK period

(4) M = OSPI_DEV_DELAY_REG[D_INIT_FLD], N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5) R = refclk

Figure 7-104 OSPI Switching Characteristics – DDR