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ZHCSN40K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

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机械数据 (封装 | 引脚)

ALF|827

散热焊盘机械数据 (封装 | 引脚)

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6.9.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode

NO.	PARAMETER		MODE^⁽¹⁵⁾	MIN	MAX	UNIT
NO.	PARAMETER		MODE^⁽¹⁵⁾	133 MHz^⁽¹⁶⁾		UNIT
GNF0	t_w(wenV)	Pulse duration, output write enable GPMC_WEn valid	div_by_1_mode;	A⁽¹⁾		ns
GNF1	t_d(csnV-wenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn valid	div_by_1_mode;	B⁽²⁾-2.55	B⁽²⁾+2.65	ns
GNF2	t_w(cleH-wenV)	Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid	div_by_1_mode;	C⁽³⁾-2.55	C⁽³⁾+2.65	ns
GNF3	t_w(wenV-dV)	Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid	div_by_1_mode;	D⁽⁴⁾-2.55	D⁽⁴⁾+2.65	ns
GNF4	t_w(wenIV-dIV)	Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid	div_by_1_mode;	E⁽⁵⁾-2.55	E⁽⁵⁾+2.65	ns
GNF5	t_{w(wenIV-cleIV)}	Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid	div_by_1_mode;	F⁽⁶⁾-2.55	F⁽⁶⁾+2.65	ns
GNF6	t_{w(wenIV-CSn[i]V)}	Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSn[i]⁽¹³⁾ invalid	div_by_1_mode;	G⁽⁷⁾-2.55	G⁽⁷⁾+2.65	ns
GNF7	t_w(aleH-wenV)	Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid	div_by_1_mode;	C⁽³⁾-2.55	C⁽³⁾+2.65	ns
GNF8	t_{w(wenIV-aleIV)}	Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid	div_by_1_mode;	F⁽⁶⁾-2.55	F⁽⁶⁾+2.65	ns
GNF9	t_c(wen)	Cycle time, write	div_by_1_mode;		H⁽⁸⁾	ns
GNF10	t_d(csnV-oenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn valid	div_by_1_mode;	I⁽⁹⁾-2.55	I⁽⁹⁾+2.65	ns
GNF13	t_w(oenV)	Pulse duration, output enable GPMC_OEn_REn valid	div_by_1_mode;		K⁽¹⁰⁾	ns
GNF14	t_c(oen)	Cycle time, read	div_by_1_mode;	L⁽¹¹⁾		ns
GNF15	t_{w(oenIV-CSn[i]V)}	Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSn[i]⁽¹³⁾ invalid	div_by_1_mode;	M⁽¹²⁾-2.55	M⁽¹²⁾+2.65	ns

(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾

(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾

(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK⁽¹⁴⁾

(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(15) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

(16) For 133 MHz:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT

DRA829J DRA829J-Q1 DRA829V DRA829V-Q1 GPMC and NAND
Flash — Command Latch Cycle

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-74 GPMC and NAND Flash — Command Latch Cycle

DRA829J DRA829J-Q1 DRA829V DRA829V-Q1 GPMC and NAND
Flash — Address Latch Cycle

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-75 GPMC and NAND Flash — Address Latch Cycle

DRA829J DRA829J-Q1 DRA829V DRA829V-Q1 GPMC and NAND
Flash — Data Read Cycle

A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.

B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.

Figure 6-76 GPMC and NAND Flash — Data Read Cycle

DRA829J DRA829J-Q1 DRA829V DRA829V-Q1 GPMC and NAND
Flash — Data Write Cycle

A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-77 GPMC and NAND Flash — Data Write Cycle

For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in the device TRM.