米6体育平台手机版

ZHCSN40K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ALF|827

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME	DESCRIPTION		MIN⁽¹⁾	NOM	MAX⁽¹⁾	UNIT
VDD_CORE	Boot/Active voltage for MAIN domain core supply		0.76	0.8	0.84	V
VDD_MCU	Boot/Active voltage for MCUSS core supply		0.76	0.8	0.89	V
VDD_CPU	Boot voltage for CPU core supply, applied at cold power up event		0.76	0.8	0.84	V
VDD_CPU	Active voltage for CPU core supply, after AVS mode enabled in software		AVS⁽⁴⁾-5%	AVS⁽⁴⁾	AVS⁽⁴⁾+5%	V
VDD_CPU AVS Range	AVS valid voltage range for VDD_CPU		0.6		0.9	V
VDDA_0P8_DLL_MMC0	MMC PLL analog supply		0.76	0.8	0.84	V
VDDAR_CORE	Main domain RAM supply		0.81	0.85	0.89	V
VDDAR_MCU	MCUSS RAM supply		0.81	0.85	0.89	V
VDDAR_CPU	CPU RAM supply		0.81	0.85	0.89	V
VDDA_0P8_DP	Displayport SERDES clock supply		0.76	0.8	0.84	V
VDDA_0P8_DP_C	Displayport SERDES clock supply		0.76	0.8	0.84	V
VDDA_0P8_DSITX	DSITX clock supply		0.76	0.8	0.84	V
VDDA_0P8_DSITX_C	DSITX clock supply		0.76	0.8	0.84	V
VDDA_0P8_CSIRX	CSIRX analog supply low		0.76	0.8	0.84	V
VDDA_0P8_SERDES0_1	SERDES0-1 analog supply low		0.76	0.8	0.84	V
VDDA_0P8_SERDES2_3	SERDES2-3 analog supply low		0.76	0.8	0.84	V
VDDA_0P8_SERDES_C0_1	SERDES0-1 clock supply		0.76	0.8	0.84	V
VDDA_0P8_SERDES_C2_3	SERDES2-3 clock supply		0.76	0.8	0.84	V
VDDA_0P8_USB	USB0-1 0.8v analog supply		0.76	0.8	0.84	V
VDDA_0P8_UFS	UFS analog supply low		0.76	0.8	0.84	V
VDDA_1P8_USB	USB0-1 1.8v analog supply		1.71	1.8	1.89	V
VDDA_1P8_UFS	UFS analog supply high		1.71	1.8	1.89	V
VDDA_1P8_DP	Displayport SERDES analog supply high		1.71	1.8	1.89	V
VDDA_1P8_DSITX	DSITX analog supply high		1.71	1.8	1.89	V
VDDA_1P8_CSIRX	CSIRX analog supply high		1.71	1.8	1.89	V
VDDA_1P8_SERDES0_1	SERDES0-1 analog supply high		1.71	1.8	1.89	V
VDDA_1P8_SERDES2_3	SERDES2-3 analog supply high		1.71	1.8	1.89	V
VDDA_3P3_USB	USB0-1 3.3v analog supply		3.14	3.3	3.46	V
VDDA_MCU_PLLGRP0	Analog supply for MCU PLL Group 0		1.71	1.8	1.89	V
VDDA_PLLGRP0	Analog supply for Main PLL Group 0		1.71	1.8	1.89	V
VDDA_PLLGRP1	Analog supply for MAIN PLL Group 1		1.71	1.8	1.89	V
VDDA_PLLGRP2	Analog supply for MAIN PLL Group 2		1.71	1.8	1.89	V
VDDA_PLLGRP3	Analog supply for MAIN PLL Group 3		1.71	1.8	1.89	V
VDDA_PLLGRP4	Analog supply for MAIN PLL Group 4		1.71	1.8	1.89	V
VDDA_PLLGRP5	Analog supply for MAIN PLL Group 5 (DDR)		1.71	1.8	1.89	V
VDDA_PLLGRP6	Analog supply for MAIN PLL Group 6		1.71	1.8	1.89	V
VDDA_0P8_PLL_MLB	MLB PLL analog supply		0.76	0.8	0.84	V
VDDA_WKUP	Oscillator supply for wkup domain		1.71	1.8	1.89	V
VDDA_ADC0	ADC analog supply		1.71	1.8	1.89	V
VDDA_ADC1	ADC analog supply		1.71	1.8	1.89	V
VDDA_0P8_PLL_DDR	DDR PLL analog supply		0.76	0.8	0.84	V
VDDA_MCU_TEMP	Analog supply for temperature sensor 0 in MCU domain		1.71	1.8	1.89	V
VDDA_POR_WKUP	WKUP domain analog supply		1.71	1.8	1.89	V
VDDA_1P8_MLB	MLB IO supply (6-pin interface)		1.71	1.8	1.89	V
VDDA_TEMP0_1	Analog supply for temperature sensor 0 and 1		1.71	1.8	1.89	V
VDDA_TEMP2_3	Analog supply for temperature sensor 2 and 3		1.71	1.8	1.89	V
VDDS_DDR^⁽²⁾	DDR inteface power supply		1.06	1.1	1.15	V
VDDS_DDR_BIAS	Bias supply for LPDDR4x		1.06	1.1	1.15	V
VDDS_DDR_C	IO power for DDR Memory Clock Bit (MCB) macro		1.06	1.1	1.15	V
VDDS_MMC0	MMC0 IO supply		1.71	1.8	1.89	V
VDDS_OSC1	HFOSC1 supply		1.71	1.8	1.89	V
VDDSHV0	IO supply for main domain general	1.8-V operation	1.71	1.8	1.89	V
VDDSHV0	IO supply for main domain general	3.3-V operation	3.14	3.3	3.46	V
VDDSHV0_MCU	IO supply MCUSS general IO group, and MCU and Main domain warm reset pins	1.8-V operation	1.71	1.8	1.89	V
VDDSHV0_MCU		3.3-V operation	3.14	3.3	3.46	V
VDDSHV1	IO supply for main domain IO group 1	1.8-V operation	1.71	1.8	1.89	V
VDDSHV1	IO supply for main domain IO group 1	3.3-V operation	3.14	3.3	3.46	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	1.8-V operation	1.71	1.8	1.89	V
VDDSHV1_MCU	IO supply for MCUSS IO group 1	3.3-V operation	3.14	3.3	3.46	V
VDDSHV2	IO supply for main domain IO group 2	1.8-V operation	1.71	1.8	1.89	V
VDDSHV2	IO supply for main domain IO group 2	3.3-V operation	3.14	3.3	3.46	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	1.8-V operation	1.71	1.8	1.89	V
VDDSHV2_MCU	IO supply for MCUSS IO group 2	3.3-V operation	3.14	3.3	3.46	V
VDDSHV3	IO supply for main domain IO group 3	1.8-V operation	1.71	1.8	1.89	V
VDDSHV3	IO supply for main domain IO group 3	3.3-V operation	3.14	3.3	3.46	V
VDDSHV4	IO supply for main domain IO group 4	1.8-V operation	1.71	1.8	1.89	V
VDDSHV4	IO supply for main domain IO group 4	3.3-V operation	3.14	3.3	3.46	V
VDDSHV5	IO supply for main domain IO group 5	1.8-V operation	1.71	1.8	1.89	V
VDDSHV5	IO supply for main domain IO group 5	3.3-V operation	3.14	3.3	3.46	V
VDDSHV6	IO supply for main domain IO group 6	1.8-V operation	1.71	1.8	1.89	V
VDDSHV6	IO supply for main domain IO group 6	3.3-V operation	3.14	3.3	3.46	V
USB0_VBUS	Voltage range for USB VBUS comparator input		0	See ⁽⁵⁾	3.46	V
USB1_VBUS	Voltage range for USB VBUS comparator input		0	See ⁽⁵⁾	3.46	V
USB0_ID	Voltage range for the USB ID input			See ⁽³⁾		V
USB1_ID	Voltage range for the USB ID input			See ⁽³⁾		V
VSS	Ground			0		V
T_J	Operating junction temperature range	Automotive	–40		125	°C
		Extended	–40		105	°C
		Commercial	0		90	°C

(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.

(2) VDDS_DDR is required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused.

(3) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source.

(4) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.

(5) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB VBUS Design Guidelines.