米6体育平台手机版

ZHCSN40K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

6.9.5.21.1.2.2 OSPI Switching Characteristics – SDR Mode

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
O7	t_c(CLK)	Cycle time, CLK	1.8V	7		ns
O7	t_c(CLK)	Cycle time, CLK	3.3V	7.5		ns
O8	t_w(CLKL)	Pulse duration, CLK low		-0.3+0.475*P ⁽²⁾		ns
O9	t_w(CLKH)	Pulse duration, CLK high		-0.3+0.475*P ⁽²⁾		ns
O10	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn active edge	1.8V	0.475 * P + 0.975 * N * R ⁽²⁾⁽³⁾ ⁽⁵⁾	0.475 * P + 0.975 * N * R + 1 ⁽³⁾ ⁽³⁾ ⁽⁵⁾	ns
O10	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn active edge	3.3V	0.475 * P + 0.975 * N * R ⁽²⁾ ⁽³⁾ ⁽⁵⁾	0.475 * P + 0.975 * N * R + 1 ⁽²⁾ ⁽³⁾ ⁽⁵⁾	ns
O11	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	1.8V	0.475 * P + 0.975 * N * R - 1 ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	0.475 * P + 0.975 * N * R + 1 ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O11	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	3.3V	-1+0.475 * P + 0.975 * N * R ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	1+0.475 * P + 0.975 * N * R ⁽²⁾ ⁽⁴⁾ ⁽⁵⁾	ns
O12	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition⁽¹⁾	1.8V	-1.16	1.25	ns
O12	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition⁽¹⁾	3.3V	-1.33	1.51	ns

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time = SCLK period

(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5) R = refclk

Figure 6-112 OSPI Switching Characteristics – SDR