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Table 6-97, Figure 6-117, Table 6-98, and Figure 6-118 present timing requirements and switching characteristics for OSPI0 Tap DDR Mode.

Table 6-97 OSPI Timing Requirements – Tap DDR Mode see Figure 6-117

NO.			MODE	MIN	MAX	UNIT
O13	t_su(D-CLK)	Setup time, OSPI0/1_D[7:0] valid before active OSPI0/1_CLK edge	No Loopback	(12.04 - (0.975T⁽¹⁾R⁽²⁾))		ns
O14	t_h(CLK-D)	Hold time, OSPI0/1_D[7:0] valid after active OSPI0/1_CLK edge	No Loopback	(1.84 + (0.975T⁽¹⁾R⁽²⁾))		ns

(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2) R = reference clock cycle time in ns

Figure 6-117 OSPI Timing Requirements – Tap DDR, No Loopback

Table 6-98 OSPI0/1 Switching Characteristics – Tap DDR Mode see Figure 6-118

NO.	PARAMETER		MIN	MAX	UNIT
O1	t_c(CLK)	Cycle time, OSPI0/1_CLK	40		ns
O2	t_w(CLKL)	Pulse duration, OSPI0/1_CLK low	((0.475P⁽¹⁾) - 0.3)		ns
O3	t_w(CLKH)	Pulse duration, OSPI0/1_CLK high	((0.475P⁽¹⁾) - 0.3)		ns
O4	t_d(CSn-CLK)	Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge	((0.475P⁽¹⁾) + ((0.975M⁽²⁾R⁽⁵⁾) - 1.5)	((0.525P⁽¹⁾) +( 1.025M⁽²⁾R⁽⁵⁾) + 1.5)	ns
O5	t_d(CLK-CSn)	Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge	((0.475P⁽¹⁾) + (0.975N⁽³⁾R⁽⁵⁾) - 1.5)	((0.525P⁽¹⁾) + (1.025N⁽³⁾R⁽⁵⁾) + 1.5)	ns
O6	t_d(CLK-D)	Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition	(–17.94 + (0.975(T⁽⁴⁾ + 1)R⁽⁵⁾))	(–1.56 + (1.025(T⁽⁴⁾ + 1)R⁽⁵⁾))	ns

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]

(5) R = reference clock cycle time in ns

Figure 6-118 OSPI Switching Characteristics – Tap DDR, No Loopback