米6体育平台手机版

ZHCSN40K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Table 6-95, Figure 6-115, Table 6-96, and Figure 6-116 present timing requirements and switching characteristics for OSPI0 Tap SDR Mode.

Table 6-95 OSPI Timing Requirements – Tap SDR Mode see Figure 6-115

NO.			MODE	MIN	MAX	UNIT
O19	t_su(D-CLK)	Setup time, OSPI_D[7:0] valid before active OSPI_CLK edge	No Loopback	(10.4 - (0.975T⁽¹⁾R⁽²⁾))		ns
O20	t_h(CLK-D)	Hold time, OSPI_D[7:0] valid after active OSPI_CLK edge	No Loopback	(–0.2 + (0.975T⁽¹⁾R⁽²⁾))		ns

(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2) R = reference clock cycle time in ns

Figure 6-115 OSPI Timing Requirements – Tap SDR, No Loopback

Table 6-96 OSPI0/1 Switching Characteristics – Tap SDR Mode see Figure 6-116

NO.	PARAMETER		MIN	MAX	UNIT
O7	t_c(CLK)	Cycle time, OSPI0/1_CLK	20		ns
O8	t_w(CLKL)	Pulse duration, OSPI0/1_CLK low	((0.475P⁽¹⁾) - 0.3)		ns
O9	t_w(CLKH)	Pulse duration, OSPI0/1_CLK high	((0.475P⁽¹⁾) - 0.3)		ns
O10	t_d(CSn-CLK)	Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge	((0.475P⁽¹⁾) + (0.975M⁽²⁾R⁽⁴⁾) - 1.5)	((0.525P⁽¹⁾) + (1.025M⁽²⁾R⁽⁴⁾) + 1.5)	ns
O11	t_d(CLK-CSn)	Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge	((0.475P⁽¹⁾) + (0.975N⁽³⁾R⁽⁴⁾) - 1.5)	((0.525P⁽¹⁾) + (1.025N⁽³⁾R⁽⁴⁾) + 1.5)	ns
O12	t_d(CLK-D)	Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition	–2	2	ns

(1) P = SCLK cycle time in ns = OSPI0/1_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4) R = reference clock cycle time in ns

Figure 6-116 OSPI Switching Characteristics – Tap SDR, No Loopback