ZHCSDA7G July 2014 – February 2018 DRV10983
PRODUCTION DATA.
| Register | Data | Description | ||
|---|---|---|---|---|
| Name | Address | Bits | ||
| SpeedCtrl1(1) | 0x00 | 7:0 | SpdCtrl[7:0] | 8 LSB of a 9-bit value used for the motor speed.
If OverRide = 1, the user can directly control the motor speed by writing to the register through I2C. |
| SpeedCtrl2(1) | 0x01 | 7 | OverRide | Use to control the SpdCtrl [8:0] bits. If OverRide = 1, the user can write the speed command through I2C. |
| 6:1 | N/A | N/A | ||
| 0 | SpdCtrl [8] | MSB of a 9-bit value used for the motor speed.
If OverRide = 1, user can directly control the motor speed by writing to the register through I2C. The MSB should be written first. Digital takes a snapshot of the MSB when LSB is written. |
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| DevCtrl(1) | 0x02 | 7:0 | enProgKey[7:0] | 8-bit byte use to enable programming in the EEPROM.
To program the EEPROM, enProgKey = 1011 0110 (0xB6), followed immediately by eeWrite = 1. Otherwise, enProgKey value is reset. |
| EECtrl(1) | 0x03 | 7 | sleepDis | Set to 1 to disable entering into sleep or standby mode. |
| 6 | SIdata | Set to 1 to enable the writing to the configuration registers. | ||
| 5 | eeRefresh | Copy EEPROM data to register. | ||
| 4 | eeWrite | Bit used to program (write) to the EEPROM. | ||
| 3:0 | N/A | N/A | ||
| Status(2) | 0x10 | 7 | OverTemp | Bit to indicate device temperature is over its limits. |
| 6 | Slp_Stdby | Bit to indicate that device went into sleep or standby mode. | ||
| 5 | OverCurr | Bit to indicate that a phase to phase overcurrent event happened. This is a sticky bit, once written, it stays high even if overcurrent signal goes low. This bit is cleared on Read. | ||
| 4 | MtrLck | Bit to indicate that the motor is locked. | ||
| 3 | N/A | N/A | ||
| 2 | N/A | N/A | ||
| 1 | N/A | N/A | ||
| 0 | N/A | N/A | ||
| Motor Speed1(2) | 0x11 | 7:0 | MotorSpeed [15:8] | 16-bit value indicating the motor speed. Always read the MotorSpeed1 first.
Velocity (Hz) = {MotorSpeed1:MotorSpeed2} / 10 For example: MotorSpeed1 = 0x01, MotorSpeed2 = 0xFF, Motor Speed = 0x01FF (511) / 10 = 51 Hz |
| Motor Speed2(2) | 0x12 | 7:0 | MotorSpeed [7:0] | |
| Motor Period1(2) | 0x13 | 7:0 | MotorPeriod [15:8] | 16-bit value indicating the motor period. Always read the MotorPeriod1 first.
tELE_PERIOD (µs) = {MotorPeriod1:MotorPeriod2} × 10 For example: MotorPeriod1 = 0x01, MotorPeriod2 = 0xFF, Motor Period = 0x01FF (511) × 10 = 5.1 ms |
| Motor Period2(2) | 0x14 | 7:0 | MotorPeriod [7:0] | |
| MotorKt1(2) | 0x15 | 7:0 | MotorKt[15:8] | 16-bit value indicating the motor measured velocity constant. Always read the MotorKt1 first.
Ktc (V/Hz)= {MotorKt1:MotorKt2} / 2 /1090 {MotorKt1:MotorKt2} corresponding to 2 × Ktph_dig |
| MotorKt2(2) | 0x16 | 7:0 | MotorKt[7:0] | |
| IPDPosition(2) | 0x19 | 7:0 | IPDPosition [7:0] | 8-bit value indicating the estimated motor position during IPD plus the IPD advance angle (see Table 7) |
| Supply Voltage(2) | 0x1A | 7:0 | SupplyVoltage [7:0] | 8-bit value indicating the supply voltage
VPOWERSUPPLY (V) = SupplyVoltage[7:0] × 30 V /256 For example, SupplyVoltage[7:0] = 0x67, VPOWERSUPPLY (V) = 0x67 (102) × 30 / 256 = 12 V |
| SpeedCmd(2) | 0x1B | 7:0 | SpeedCmd[7:0] | 8-bit value indicating the speed command based on analog or PWMin or I2C.
FF indicates 100% speed command. |
| spdCmd Buffer(2) | 0x1C | 7:0 | spdCmdBuffer [8:1] | 8-bit value indicating the speed command after buffer output.
FF indicates 100% speed command. |
| FaultCode(2) | 0x1E | 7:6 | N/A | N/A |
| 5 | Lock5 | Stuck in closed loop | ||
| 4 | Lock4 | Stuck in open loop | ||
| 3 | Fault3 | No motor | ||
| 2 | Lock2 | Kt abnormal | ||
| 1 | Lock1 | Speed abnormal | ||
| 0 | Lock0 | Lock detection current limit | ||
| Motor Param1(3) | 0x20 | 7 | DoubleFreq | 0 = Set driver output frequency to 25 kHz
1 = Set driver output frequency to 50 kHz |
| 6:0 | Rm[6:0] | Rm[6:4] : Number of the Shift bits of the motor phase resistance
Rm[3:0] : Significant value of the motor phase resistance Rmdig = R_(ph_ct) / 0.00967 Rmdig = Rm[3:0] ≪ Rm[6:4] SeeMotor Phase Resistance and Table 2 |
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| Motor Param2(3) | 0x21 | 7 | AdjMode | Closed loop adjustment mode setting
0 = Full cycle adjustment 1 = Half cycle adjustment |
| 6:0 | Kt[6:0] | Kt[6:4] = Number of the Shift bits of BEMF constant
Kt[3:0] = Significant value of the BEMF constant 〖Kt〗_(ph_dig) = 1090×〖Kt〗_ph 〖Kt〗_(ph_dig) = Kt[3:0] ≪ Kt[4:6] See BEMF Constant and Table 3. |
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| Motor Param3(3) | 0x22 | 7 | CtrlAdvMd | Motor commutate control advance
0 = Fixed time 1 = Variable time relative to the motor speed and VCC |
| 6:0 | Tdelay[6:0] | tdelay [6:4] = Number of the Shift bits of LRTIME
tdelay [3:0] = Significant value of LRTIME tSETTING = 2.5 µs × {TCtrlAdv[3:0] << TCtrlAdv[6:4]} |
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| SysOpt1(3) | 0x23 | 7:6 | ISDThr[1:0] | ISD stationary judgment threshold
00 = 6 Hz (80 ms, no zero cross) 01 = 3 Hz (160 ms, no zero cross) 10 = 1.6 Hz (320 ms, no zero cross) 11 = 0.8 Hz (640 ms, no zero cross) |
| 5:4 | IPDAdvcAgl [1:0] | Advancing angle after inductive sense
00 = 30° 01 = 60° 10 = 90° 11 = 120° |
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| 3 | ISDen | 0 = Initial speed detect (ISD) disable
1 = ISD enable |
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| 2 | RvsDrEn | 0 = Reverse drive disable
1 = Reverse drive enable |
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| 1:0 | RvsDrThr[1:0] | The threshold where device starts to process reverse drive (RvsDr) or brake.
00 = 6.3 Hz 01 = 13 Hz 10 = 26 Hz 11 = 51 Hz |
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| SysOpt2(3) | 0x24 | 7:6 | OpenLCurr[1:0] | Open loop current setting.
00 = 0.2 A 01 = 0.4 A 10 = 0.8 A 11 = 1.6 A |
| 5:3 | OpLCurrRt:[2:0] | Open-loop current ramp-up rate setting
000 = 6 VCC/s 001 = 3 VCC/s 010 = 1.5 VCC/s 011 = 0.7 VCC/s 100 = 0.34 VCC/s 101 = 0.16 VCC/s 110 = 0.07 VCC/s 111 = 0.023 VCC/s |
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| 2:0 | BrkDoneThr [2:0] | Braking mode setting
000 = No brake (BrkEn = 0) 001 = 2.7 s 010 = 1.3 s 011 = 0.67 s 100 = 0.33 s 101 = 0.16 s 110 = 0.08 s 111 = 0.04 s |
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| SysOpt3(3) | 0x25 | 7:6 | CtrlCoef[1:0] | Control coefficient
00 = 0.25 01 = 0.5 10 = 0.75 11 = 1 |
| 5:3 | StAccel2[2:0] | Open loop start-up accelerate (second order)
000 = 57 Hz/s2 001 = 29 Hz/s2 010 = 14 Hz/s2 011 = 6.9 Hz/s2 100 = 3.3 Hz/s2 101 = 1.6 Hz/s2 110 = 0.66 Hz/s2 111 = 0.22 Hz/s2 |
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| 2:0 | StAccel[2:0] | Open loop start-up accelerate (first order)
000 = 76 Hz/s 001 = 38 Hz/s 010 = 19 Hz/s 011 = 9.2 Hz/s 100 = 4.5 Hz/s 101 = 2.1 Hz/s 110 = 0.9 Hz/s 111 = 0.3 Hz/s |
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| SysOpt4(3) | 0x26 | 7:3 | Op2ClsThr[4:0] | Open to closed loop threshold
0xxxx = Range 0: n × 0.8 Hz 00000 = N/A 00001 = 0.8 Hz 00111 = 5.6 Hz 01111 = 12 Hz 1xxxx = Range 1: (n + 1) × 12.8 Hz 10000 = 12.8 Hz 10001 = 25.6 Hz 10111 = 192 Hz 11111 = 204.8 Hz |
| 2:0 | AlignTime[2:0] | Align time.
000 = 5.3 s 001 = 2.7 s 010 = 1.3 s 011 = 0.67 s 100 = 0.33 s 101 = 0.16 s 110 = 0.08 s 111 = 0.04 s |
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| SysOpt5(3) | 0x27 | 7 | FaultEn3 (LockEn[3]) | No motor fault. Enabled when high |
| 6 | LockEn[2] | Abnormal Kt. Enabled when high | ||
| 5 | LockEn[1] | Abnormal speed. Enabled when high | ||
| 4 | LockEn[0] | Lock detection current limit. Enabled when high | ||
| 3 | AVSIndEn | Inductive AVS enable. Enabled when high. | ||
| 2 | AVSMEn | Mechanical AVS enable. Enabled when high | ||
| 1 | AVSMMd | Mechanical AVS mode
0 = AVS to VCC 1 = AVS to 24 V |
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| 0 | IPDRlsMd | IPD release mode
0 = Brake when inductive release 1 = Hi-z when inductive release |
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| SysOpt6(3) | 0x28 | 7:4 | SWiLimitThr [3:0] | Acceleration current limit threshold
0000 = No acceleration current limit 0001 = 0.2-A current limit xxxx = n × 0.2 A current limit |
| 3:1 | HWiLimitThr [2:0] | Lock detection current limit threshold
(n + 1) × 0.4 A |
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| 0 | N/A | N/A | ||
| SysOpt7(3) | 0x29 | 7 | LockEn[5] | Stuck in closed loop (no zero cross detected). Enabled when high |
| 6:4 | ClsLpAccel[2:0] | Closed loop accelerate
000 = Inf fast 001 = 48 VCC/s 010 = 48 VCC/s 011 = 0.77 VCC/s 100 = 0.37 VCC/s 101 = 0.19 VCC/s 110 = 0.091 VCC/s 111 = 0.045 VCC/s |
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| 3:0 | Deadtime[3:0] | Dead time between HS and LS gate drive for motor phases
0000 = 40 ns xxxx = (n + 1) × 40 ns. Recommended minimum dead time is 400 ns for 24-V VCC and 360 ns for 12-V VCC. |
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| SysOpt8(3) | 0x2A | 7:4 | IPDCurrThr[3:0] | IPD (inductive sense) current threshold
0000 = No IPD function. Align and Go 0001 = 0.4-A current threshold. xxxx = 0.2 A × (n + 1) current threshold. |
| 3 | LockEn[4] | Open loop stuck (no zero cross detected). Enabled when high | ||
| 2 | VregSel | Buck regulator voltage select
0: Vreg = 5 V 1: Vreg = 3.3 V |
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| 1:0 | IPDClk[1:0] | Inductive sense clock
00 = 12 Hz; 01 = 24 Hz; 10 = 47 Hz; 11 = 95 Hz |
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| SysOpt9(3) | 0x2B | 7:6 | FGOLsel[1:0] | FG open loop output select
00 = FG outputs in both open loop and closed loop 01 = FG outputs only in closed loop 10 = FG outputs closed loop and the first open loop 11 = Reserved |
| 5:4 | FGcycle[1:0] | FG cycle select
00 = 1 pulse output per electrical cycle 01 = 2 pulses output per 3 electrical cycles 10 = 1 pulse output per 2 electrical cycles 11 = 1 pulse output per 3 electrical cycles |
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| 3:2 | KtLckThr[1:0] | Abnormal Kt lock detect threshold
00 = Kt_high = 3/2Kt. Kt_low = 3/4Kt 01 = Kt_high = 2Kt. Kt_low = 3/4Kt 10 = Kt_high = 3/2Kt. Kt_low = 1/2Kt 11 = Kt_high = 2Kt. Kt_low = 1/2Kt |
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| 1 | SpdCtrlMd | Speed input mode
0 = Analog input expected at SPEED pin 1 = PWM input expected at SPEED pin |
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| 0 | CLoopDis | 0 = Transfer to closed loop at Op2ClsThr speed
1 = No transfer to closed loop. Keep in open loop |
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