ZHCSFB0D June 2016 – November 2023 DRV2510-Q1
PRODUCTION DATA
As shown in Figure 7-5, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read-write bit. The read-write bit determines the direction of the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I2C device address and the read-write bit, the DRV2510-Q1 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the DRV2510-Q1 internal-memory address that is accessed. After receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.