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ZHCSEH1A December 2015 – December 2015 DRV2625

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

YFF|9
- MXBG144B

散热焊盘机械数据 (封装 | 引脚)

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Supply Voltage	V_DD	–0.3	6	V
Input voltage	NRST	–0.3	6	V
	SDA	–0.3	6	V
	SCL	–0.3	6	V
	TRIG/INTZ	–0.3	6	V
Operating free-air temperature range, T_A		–40	85	°C
Operating junction temperature range, T_J		–40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			MIN	MAX	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–1500	1500	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD	Supply voltage	2.7	5.5	V
R_L	Load impedance	8		Ω
C_L	Load capacitance		100	pF
ƒ_(LRA)	LRA frequency	45	300	Hz

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DRV2625	UNIT
		DSBGA
		9 PINS
R_θJA	Junction-to-ambient thermal resistance	107	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.9	°C/W
R_θJB	Junction-to-board thermal resistance	18.1	°C/W
ψ_JT	Junction-to-top characterization parameter	3.8	°C/W
ψ_JB	Junction-to-board characterization parameter	18.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_A = 25 °C, V_DD = 3.6 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_(REG)	Voltage at the REG pin			1.84		V
I_IL	Digital low-level input current	NRST, TRIG/INTZ, SDA, SCL V_DD = 5.5 V, V_I = 0 V			100	nA
I_IH	Digital high-level input current	SDA, SCL V_DD = 5.5 V, V_I = V_DD			0.1	µA
		NRST V_DD = 5.5 V, V_I = V_DD			1
		TRIG/INTZ V_DD = 5.5 V, V_I = V_DD		2.7	3.5
V_IL	Digital low-level input voltage	NRST, TRIG/INTZ, SDA, SCL			0.4	V
V_IH	Digital high-level input voltage	NRST, TRIG/INTZ, SDA, SCL	1.41			V
V_OL	Digital low-level output voltage	TRIG/INTZ, SDA 3-mA sink current			0.4	V
R_DS(on)	Drain-source on-state resistance (LS + HS)			0.75		Ω
I_(SD)	Shutdown current	V_(NRST) = 0 V		105	180	nA
I_(STBY)	Standby current	V_(NRST) = V_DD In stand-by mode		1.55	2	µA
I_(Q)	Quiescent current	V_(NRST) = V_DD In idle mode - no signal		2.5		mA
Z_O(SD)	Output impedance in shutdown	OUT+ to GND, OUT– to GND		15		kΩ
Z_O(STBY)	Output impedance in standby	OUT+ to GND, OUT– to GND		15		kΩ
Z_LOAD(th)	Load impedance threshold for over-current detection	OUT+ to GND, OUT– to GND		4		Ω

6.6 Timing Requirements

T_A = 25 °C, V_DD = 3.6 V (unless otherwise noted)

		MIN	MAX	UNIT
ƒ_(SCL)	Frequency at the SCL pin with no wait states		400	kHz
t_w(H)	Pulse duration, SCL high	0.6		µs
t_w(L)	Pulse duration, SCL low	1.3		µs
t_su(1)	Setup time, SDA to SCL	100		ns
t_h(1)	Hold time, SCL to SDA	10		ns
t_(BUF)	Bus free time between stop and start condition	1.3		µs
t_su(2)	Setup time, SCL to start condition	0.6		µs
t_h(2)	Hold time, start condition to SCL	0.6		µs
t_su(3)	Setup time, SCL to stop condition	0.6		µs

6.7 Switching Characteristics

T_A = 25 °C, V_DD = 3.6 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
t_(on)	Device startup time	from shutdown standby	1	ms
t_(start)	Waveform startup time	from trigger to output signal	1	ms
f_O(PWM)	PWM output frequency (in OUT+ and OUT-)		20.5	kHz

Figure 1. SCL and SDA Timing

DRV2625 i2c_start_stop_timing_slos879.gif

Figure 2. Timing for Start and Stop Conditions

6.8 Typical Characteristics

DRV2625 Fig12_Standby_Current_vs_VDD.png

Figure 3. Standby Current vs Supply Voltage

DRV2625 Fig1_ERM_Click_Ext_Pulse_Trigger.png

V_DD = 3.6 V

Figure 5. ERM Click (Open-Loop) with External Pulse-Trigger

DRV2625 Fig3_ERM_Click_Bounce_Int_Trigger.png

V_DD = 3.6 V

Figure 7. ERM Click-Bounce (Open-Loop) with Internal Trigger

V_DD = 3.6 V

Figure 9. ERM RTP Buzz (Closed-Loop) with Pulse-Trigger

V_DD = 3.6 V

Figure 11. LRA Squarewave Click (Open-Loop) with Automatic Braking

V_DD = 3.6 V

Figure 13. LRA SimpleDrive with Closed-Loop

DRV2625 Fig6_Startup_Latency_for_ERM_and_LRA.png

V_DD = 3.6 V

Figure 4. Startup Latency for ERM and LRA

DRV2625 Fig2_LRA_Strong_Click_Internal.png

V_DD = 3.6 V

Figure 6. LRA Strong Click (Closed-Loop) with External Level-Trigger

DRV2625 Fig4_LRA_Transition_Click_1_Internal.png

V_DD = 3.6 V

Figure 8. LRA Transition Click (Closed-Loop) with Internal Trigger

V_DD = 3.6 V

Figure 10. LRA Sinewave Click (Open-Loop) with Automatic Braking

DRV2625 Fig10_ERM_OL_Click_with_Autobrake.png

V_DD = 3.6 V

Figure 12. ERM Click (Open-Loop) with Automatic Braking

V_DD = 3.6 V

Figure 14. LRA SimpleDrive with Sinewave