ZHCS343C May 2012 – January 2023 DRV2665
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEV_RST[0] | STANDBY[0] | Reserved | TIMEOUT[1:0] | EN_OVERRIDE[0] | Reserved | ||
R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 |
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION | |
---|---|---|---|---|---|
7 | DEV_RST | R/W | 0 | When asserted, the device will immediately stop any transaction in process, reset all of its internal register to their default values, and enters standby mode. | |
0 | Normal operation | ||||
1 | Reset device | ||||
6 | STANDBY | R/W | 1 | Low-power standby | |
0 | Device is active and ready to receive a signal. | ||||
1 | Device is in low power standby mode. | ||||
5-4 | Reserved | ||||
3-2 | TIMEOUT[1:0] | R/W | 0 | Time period when the FIFO runs empty and the device goes into idle mode, powering down the boost converter and amplifier. | |
0 | 5 ms | ||||
1 | 10 ms | ||||
2 | 15 ms | ||||
3 | 20 ms | ||||
1 | EN_OVERRIDE | R/W | 0 | Override bit for the boost converter and amplifier enables. | |
0 | Boost converter and amplifier enables are controlled by device logic. | ||||
1 | Boost converter and amplifier are enabled indefinitely. | ||||
0--1 | Reserved |