The flyback circuit is intended for applications using piezo valves, piezo polymers, and other high-voltage loads. The previously listed applications go from ±100 V, however this circuit can go up to even higher voltages (1 kV for example) depending on the feedback network and maximum operating conditions of the external components. The input is controlled using PWM, a DAC, or a purely analog signal. Therefore, a proper input filter may be required as discussed in the previous application circuits.

The increased voltage range, however, comes at a price. As the output voltage increases, the capable output sourcing current is lowered. However, because most piezo loads require a small current for the holding or blocking force, the drop in current may not impact the performance of the application. Figure 8-16 shows a typical flyback circuit.

Figure 8-16 Flyback Circuit

The following sections shown in Figure 8-16 must be explained:

• Op-amp integrator
• Comparator and pulldown FET
• C_(HV) value

The op-amp integrator shown at the bottom of the circuit in Figure 8-16, is used to control the output voltage. Because the input can be a PWM or DAC signal, it helps smooth out the input signal. Additionally, the output controls the virtual ground of the feedback network. For example, when the output of the integrator is equal to V_OL (approximately 0 V), the current through R_(FB2) is at the maximum and therefore increase the current (and voltage) on R_(FB1) which raises the voltage across the piezo load. Likewise, as the output voltage of the integrator increases, it then decreases the current through R_(FB2) and therefore decreases the voltage on R_(FB1), which lowers the voltage across the piezo load.

The comparator and pulldown FET are used to drain the charge on the high-voltage output. Because a high resistance (or low current) is desired through for the feedback network, the RC-time constant of draining charge can be very long. To help with this long RC-time constraint, the comparator and pulldown FET are added to drain charge when V_FB > V_ref which adds a low resistance in parallel and therefore lowers the RC time constant. Ensure that this pulldown network can support the voltage and the current. As shown in Figure 8-9 and Figure 8-10, the pulldown allows for better regulation and faster stopping time.

Lastly, the C_(HV) value is determined by the system. A value of >1-nF total capacitance is required on the high-voltage node for proper regulation. This total capacitance is the combination of the piezo load and the onboard C_(HV).