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ZHCSEF5G May 2014 – September 2016 DRV5033

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

DBZ|3
- MPDS108G
LPG|3
- MPBC003B

散热焊盘机械数据 (封装 | 引脚)

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7 Detailed Description

7.1 Overview

The DRV5033 device is a chopper-stabilized hall sensor with a digital omnipolar switch output for magnetic sensing applications. The DRV5033 device can be powered with a supply voltage between 2.5 and 38 V, and will survive –22 V reverse battery conditions continuously. Note that the DRV5033 device will not be operating when about –22 to 2.4 V is applied to V_CC (with respect to GND). In addition, the device can withstand voltages up to 40 V for transient durations.

The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field.

The omnipolar configuration allows the hall sensor to respond to either a south or north pole. A strong magnetic field of either polarity will cause the output to pull low (operate point, B_OP), and a weaker magnetic field will cause the output to release (release point, B_RP). Hysteresis is included in between the operate and release points, so magnetic field noise will not trip the output accidentally.

An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to V_CC, or to a different voltage supply. This allows for easier interfacing with controller circuits.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Field Direction Definition

A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 11.

N = North pole, S = South pole

Figure 11. Field Direction Definition

7.3.2 Device Output

If the device is powered on with a magnetic field strength between B_RP and B_OP, then the device output is indeterminate and can either be Hi-Z or Low. If the field strength is greater than B_OP, then the output is pulled low. If the field strength is less than B_RP, then the output is released.

Figure 12. DRV5033—B_OP > 0

7.3.3 Power-On Time

After applying V_CC to the DRV5033 device, t_on must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 13 and Figure 14 occurs at the end of t_on. This pulse can allow the host processor to determine when the DRV5033 output is valid after startup. In Case 1 (Figure 13) and Case 2 (Figure 14), the output is defined assuming a constant magnetic field B > B_OP and B < B_RP.

Figure 13. Case 1: Power On When B > B_OP

Figure 14. Case 2: Power On When B < B_RP

If the device is powered on with the magnetic field strength B_RP < B < B_OP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until t_on has elapsed. At the end of t_on, a pulse is given on the OUT pin to indicate that t_on has elapsed. After t_on, if the magnetic field changes such that B_OP < B, the output is released. Case 3 (Figure 15) and Case 4 (Figure 16) show examples of this behavior.

Figure 15. Case 3: Power On When B_RP < B < B_OP, Followed by B > B_OP

Figure 16. Case 4: Power On When B_RP < B < B_OP, Followed by B < B_RP

7.3.4 Output Stage

The DRV5033 output stage uses an open-drain NMOS, and it is rated to sink up to 30 mA of current. For proper operation, calculate the value of the pullup resistor R1 using Equation 1.

Equation 1. DRV5033 eq_01_slis150.gif

The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching.

In addition, ensure that the value of R1 > 500 Ω to ensure the output driver can pull the OUT pin close to GND.

NOTE

V_ref is not restricted to V_CC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings.

Figure 17.

Select a value for C2 based on the system bandwidth specifications as shown in Equation 2.

Equation 2. DRV5033 eq_02_slis150.gif

Most applications do no require this C2 filtering capacitor.

7.3.5 Protection Circuits

The DRV5033 device is fully protected against overcurrent and reverse-supply conditions.

7.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to I_OCP. During this clamping, the r_DS(on) of the output FET is increased from the nominal value.

7.3.5.2 Load Dump Protection

The DRV5033 device operates at DC V_CC conditions up to 38 V nominally, and can additionally withstand V_CC = 40 V. No current-limiting series resistor is required for this protection.

7.3.5.3 Reverse Supply Protection

The DRV5033 device is protected in the event that the V_CC pin and the GND pin are reversed (up to –22 V).

NOTE

In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.

Table 1.

FAULT	CONDITION	DEVICE	DESCRIPTION	RECOVERY
FET overload (OCP)	I_SINK ≥ I_OCP	Operating	Output current is clamped to I_OCP	I_O < I_OCP
Load dump	38 V < V_CC < 40 V	Operating	Device will operate for a transient duration	V_CC ≤ 38 V
Reverse supply	–22 V < V_CC < 0 V	Disabled	Device will survive this condition	V_CC ≥ 2.5 V

7.4 Device Functional Modes

The DRV5033 device is active only when V_CC is between 2.5 and 38 V.

When a reverse supply condition exists, the device is inactive.