SLVSH22 May 2024 DRV8000-Q1

ADVANCE INFORMATION

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10 DRV8000-Q1_CNFG Registers

Table 10-1 lists the memory-mapped registers for the DRV8000-Q1_CNFG registers. All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.

Table 10-1 DRV8000-Q1_CNFG Registers

Offset	Acronym	Register Name	Section
9h	IC_CNFG1	IC configuration register 1.	Section 10.1
Ah	IC_CNFG2	IC configuration register 2.	Section 10.2
Bh	GD_CNFG	Gate driver configuration register.	Section 10.3
Ch	GD_IDRV_CNFG	IDRIVE setting configuration register.	Section 10.4
Dh	GD_VGS_CNFG	VGS detection configuration register.	Section 10.5
Eh	GD_VDS_CNFG	VDS monitoring configuration register.	Section 10.6
Fh	GD_CSA_CNFG	CSA configuration register.	Section 10.7
10h	GD_AGD_CNFG	Advanced smart gate driver configuration register.	Section 10.8
11h	GD_PDR_CNFG	Propagation Delay Reduction configuration register.	Section 10.9
12h	GD_STC_CNFG	Slew time control configuration register.	Section 10.10
13h	GD_SPARE_CNFG1	Spare gate driver configuration register 1.	Section 10.11
14h	HB_ITRIP_DG	Half-bridge ITRIP deglitch configuration register 2.	Section 10.12
15h	HB_OUT_CNFG1	Half-bridge output 5 and 6 configuration register.	Section 10.13
16h	HB_OUT_CNFG2	Half-bridge output 1-4 configuration register.	Section 10.14
17h	HB_OCP_CNFG	Half-bridge overcurrent deglitch configuration register.	Section 10.15
18h	HB_OL_CNFG1	Half-bridge active and passive open-load enable register	Section 10.16
19h	HB_OL_CNFG2	Half-bridge active open-load threshold select register.	Section 10.17
1Ah	HB_SR_CNFG	Haf-bridge slew rate configuration register.	Section 10.18
1Bh	HB_ITRIP_CNFG	Half-bridge ITRIP configuration register 1.	Section 10.19
1Ch	HB_ITRIP_FREQ	Half-bridge ITRIP frequency configuration register 2.	Section 10.20
1Dh	HS_HEAT_OUT_CNFG	High-side and heater driver output configuration register.	Section 10.21
1Eh	HS_OC_CNFG	High-side driver overcurrent threshold configuration register.	Section 10.22
1Fh	HS_OL_CNFG	High-side driver open load threshold configuration register.	Section 10.23
20h	HS_REG_CNFG1	High-side driver regulation configuration register.	Section 10.24
21h	HS_REG_CNFG2	High-side driver regulation configuration register.	Section 10.25
22h	HS_PWM_FREQ_CNFG	High-side driver PWM generator frequency configuration register.	Section 10.26
23h	HEAT_CNFG	Heater configuration register.	Section 10.27
24h	EC_CNFG	Electrochrome configuration register.	Section 10.28
25h	HS_OCP_DG	High-side driver regulation configuration register.	Section 10.29
26h	SPARE_CNFG2	Spare configuration 2.	Section 10.30
27h	SPARE_CNFG3	Spare configuration 3.	Section 10.31
28h	SPARE_CNFG4	Spare configuration 4.	Section 10.32

Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.

Table 10-2 DRV8000-Q1_CNFG Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

10.1 IC_CNFG1 Register (Offset = 9h) [Reset = 0002h]

IC_CNFG1 is shown in Table 10-3.

Return to the Summary Table.

Includes configurations charge pump and watchdog, and fault levels and reactions for supply, charge pump, thermal, and watch dog faults.

Table 10-3 IC_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	OTSD_MODE	R/W	0h	Sets overtemperature shutdown behavior. If any thermal cluster reaches OT, the device will either shut down all drivers or affected drivers only (drivers in zone 3, for example). 0b = Global shutdown. 1b = Affected driver shutdown only.
14	DIS_CP	R/W	0h	When EN_GD = 0, the charge pump can be disabled, putting the device in a communication only mode. 0b = Charge pump enabled. 1b = Charge pump disabled.
13-12	PVDD_OV_MODE	R/W	0h	PVDD supply overvoltage monitor mode. 00b = Latched fault. 01b = Automatic recovery. 10b = Warning report only. 11b = Disabled.
11-10	PVDD_OV_DG	R/W	0h	PVDD supply overvoltage monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs
9	PVDD_OV_LVL	R/W	0h	PVDD supply overvoltage monitor threshold. 0b = 21.5 V 1b = 28.5 V
8	VCP_UV_LVL	R/W	0h	VCP charge pump undervoltage monitor threshold. 0b = 4.75 V 1b = 6.25 V
7-6	CP_MODE	R/W	0h	Charge pump operating mode. 00b = Automatic switch between tripler and doubler mode. 01b = Always doubler mode. 10b = Always tripler mode. 11b = RSVD
5	VCP_UV_MODE	R/W	0h	VCP charge pump undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery.
4	PVDD_UV_MODE	R/W	0h	PVDD supply undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery.
3	WD_EN	R/W	0h	Watchdog timer enable. 0b = Watchdog timer disabled. 1b = Watchdog dog timer enabled.
2	WD_FLT_M	R/W	0h	Watchdog fault mode. Watchdog fault is cleared by CLR_FLT. 0b = Watchdog fault is reported to WD_FLT and WARN register bits. Drivers remain enabled and FAULT bit is not asserted. 1b = Watchdog fault is reported to WD_FLT and FAULT register bits. All drivers are disabled in response to watchdog fault.
1	WD_WIN	R/W	1h	Watchdog timer window. 0b = 4 to 40 ms 1b = 10 to 100 ms
0	EN_SSC	R/W	0h	Spread spectrum clocking. 0b = Disabled. 1b = Enabled.

10.2 IC_CNFG2 Register (Offset = Ah) [Reset = 0000h]

IC_CNFG2 is shown in Table 10-4.

Return to the Summary Table.

Includes thermal cluster warning disable bits.

Table 10-4 IC_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	ZONE4_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 4. Enabled = 0b Disabled = 1b
6	ZONE3_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 3. Enabled = 0b Disabled = 1b
5	ZONE2_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 2. Enabled = 0b Disabled = 1b
4	ZONE1_OTW_H_DIS	R/W	0h	Disables the high overtemperature warning for zone 1. Enabled = 0b Disabled = 1b
3	ZONE4_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 4. Enabled = 0b Disabled = 1b
2	ZONE3_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 3. Enabled = 0b Disabled = 1b
1	ZONE2_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 2. Enabled = 0b Disabled = 1b
0	ZONE1_OTW_L_DIS	R/W	0h	Disables the low overtemperature warning for zone 1. Enabled = 0b Disabled = 1b

10.3 GD_CNFG Register (Offset = Bh) [Reset = 0000h]

GD_CNFG is shown in Table 10-5.

Return to the Summary Table.

General gate driver controls. Includes gate driver enable, bridge configuration, input pin modes, and open load enable.

Table 10-5 GD_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	IDRV_LO1	R/W	0h	Enable low current IDRVN and IDRVP mode for half-bridge 1. 0b = IDRVP_1 and IDRVN_1 utilize standard values. 1b = IDRVP_1 and IDRVN_1 utilize low current values.
12	IDRV_LO2	R/W	0h	Enable low current IDRVN and IDRVP mode for half-bridge 2. 0b = IDRVP_2 and IDRVN_2 utilize standard values. 1b = IDRVP_2 and IDRVN_2 utilize low current values.
11	PU_SH_1	R/W	0h	Gate driver 1 pull up diagnostic current source. Set EN_OLSC = 1b to use. 0b = Disabled. 1b = Enabled.
10	PD_SH_1	R/W	0h	Gate driver 1 pull down diagnostic current source. Set EN_OLSC = 1b to use. 0b = Disabled. 1b = Enabled.
9	PU_SH_2	R/W	0h	Gate driver 2 pull up diagnostic current source. Set EN_OLSC = 1b to use. 0b = Disabled. 1b = Enabled.
8	PD_SH_2	R/W	0h	Gate driver 2 pull down diagnostic current source. Set EN_OLSC = 1b to use. 0b = Disabled. 1b = Enabled.
7	RESERVED	R	0h	Reserved
6	IN2_MODE	R/W	0h	Sets gate driver 2 control source. 0b = Input pin IN2. 1b = SPI control bit S_IN2.
5	IN1_MODE	R/W	0h	Sets gate driver 1 control source. 0b = Input pin IN1. 1b = SPI control bit S_IN1.
4	BRG_FW	R/W	0h	Gate driver 1 and 2 control freewheeling setting. Settings shared between half-bridges 1 and 2. 0b = Low-side freewheeling. 1b = High-side freewheeling.
3-2	BRG_MODE	R/W	0h	Gate driver 1 and 2 input control mode. 00b = Independent half-bridge input control. 01b = PH/EN H-bridge input control. 10b = PWM H-bridge input control.
1	EN_OLSC	R/W	0h	Offline open load and short circuit diagnostic enable. 0b = Disabled. 1b = VDS monitors set into real-time voltage monitor mode and diagnostics current sources enabled.
0	EN_GD	R/W	0h	Enable gate driver bit 0b = Driver inputs are ignored and the gate driver passive pull-downs are enabled. 1b = Gate driver outputs are enabled and controlled by the digital inputs.

10.4 GD_IDRV_CNFG Register (Offset = Ch) [Reset = FFFFh]

GD_IDRV_CNFG is shown in Table 10-6.

Return to the Summary Table.

Includes IDRIVE drive current levels for each half-bridge gate driver.

Table 10-6 GD_IDRV_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	IDRVP_1	R/W	Fh	Gate driver 1 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO1). 0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA)
11-8	IDRVN_1	R/W	Fh	Gate driver 1 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO1). 0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA)
7-4	IDRVP_2	R/W	Fh	Gate driver 2 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO2). 0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA)
3-0	IDRVN_2	R/W	Fh	Gate driver 2 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO2). 0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA)

10.5 GD_VGS_CNFG Register (Offset = Dh) [Reset = 0030h]

GD_VGS_CNFG is shown in Table 10-7.

Return to the Summary Table.

VGS fault detection configurations.

Table 10-7 GD_VGS_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	VGS_IND	R/W	0h	VGS independent shutdown mode enable. Active for BRG_MODE = 00b, 11b. 0b = Disabled. 1b = Enabled. VGS gate fault will only shutdown the associated half-bridge.
10-9	VGS_TDEAD	R/W	0h	Insertable digital dead-time. 00b = 0 ns 01b = 2 µs 10b = 4 µs 11b = 8 µs
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6-4	VGS_TDRV	R/W	3h	VGS drive time and VDS monitor blanking time. 000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs
3	VGS_HS_DIS	R/W	0h	VGS monitor based dead-time handshake. 0b = Enabled. 1b = Disabled. Gate drive transition based on tDRIVE and tDEAD time duration
2	VGS_LVL	R/W	0h	VGS monitor threshold for dead-time handshake and gate fault detection. 0b = 1.4 V. 1b = 1.0 V
1-0	VGS_MODE	R/W	0h	VGS gate fault monitor mode. 00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled.

10.6 GD_VDS_CNFG Register (Offset = Eh) [Reset = 0D2Dh]

GD_VDS_CNFG is shown in Table 10-8.

Return to the Summary Table.

VDS monitoring or short-circuit detection configuration register.

Table 10-8 GD_VDS_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD	R/W	0h	Reserved.
14	VDS_IND	R/W	0h	VDS fault independent shutdown mode configuration. 0b = Disabled. VDS fault will shut down all gate drivers. 1b = Enabled. VDS gate fault will only shutdown the associated gate driver.
13-12	VDS_IDRVN	R/W	0h	IDRVN gate pull-down current after VDS_OCP fault for gate driver 1 and 2. 00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA
11-8	VDS_LVL_1	R/W	Dh	Gate Driver 1 HS and LS VDS overcurrent monitor threshold. 0000b = 0.06 V 00001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V
7-6	VDS_MODE	R/W	0h	VDS overcurrent monitor mode. 00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled.
5-4	VDS_DG	R/W	2h	VDS overcurrent monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs
3-0	VDS_LVL_2	R/W	Dh	Gate Driver 2 HS and LS VDS overcurrent monitor threshold. 0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V

10.7 GD_CSA_CNFG Register (Offset = Fh) [Reset = 0004h]

GD_CSA_CNFG is shown in Table 10-9.

Return to the Summary Table.

CSA configurations and controls.

Table 10-9 GD_CSA_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7-5	CSA_BLK	R/W	0h	Current shunt amplifier blanking time. % of tDRV. 000b = 0 %, Disabled 001b = 25 % 010b = 37.5 % 011b = 50 % 100b = 62.5 % 101b = 75 % 110b = 87.5 % 111b = 100 %
4	CSA_BLK_SEL	R/W	0h	Current shunt amplifier blanking trigger source. 0b = Gate driver 1 1b = Gate driver 2
3-2	CSA_GAIN	R/W	1h	Current shunt amplifier gain setting. 00b = 10 V/V 01b = 20 V/V 10b = 40 V/V 11b = 80 V/V
1	CSA_DIV	R/W	0h	Current shunt amplifier internal reference voltage divider. 0b = VREF / 2 1b = VREF / 8
0	RESERVED	R	0h	Reserved

10.8 GD_AGD_CNFG Register (Offset = 10h) [Reset = 0402h]

GD_AGD_CNFG is shown in Table 10-10.

Return to the Summary Table.

Includes Advanced smart gate driver configurations, enables for DCC and PDR, post-charge settings.

Table 10-10 GD_AGD_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	PDR_ERR	R/W	0h	PDR loop error limit for gate driver 1 and 2. 0b = 1-bit error 1b = Actual error
13-12	AGD_ISTRONG	R/W	0h	Adaptive gate driver ISTRONG configuration. 00b = ISTRONG pull-down decoded from initial IDRVP_x register setting. 01b = 62 mA 10b = 124 mA 11b = RSVD
11-10	AGD_THR	R/W	1h	Adaptive gate driver VSH threshold configuration. 00b = 1V, VPVDD - 0.5V 01b = 1V, VPVDD - 1V 10b = 2V, VPVDD - 1.5V 11b = 2V, VPVDD - 2V
9	SET_AGD	R/W	0h	Set active half-bridge for adaptive gate drive control loops. 0b = Gate driver 1 1b = Gate driver 2
8	FW_MAX	R/W	0h	Gate drive current used for freewheeling MOSFET for gate driver 1 and 2. 0b = PRE_CHR_MAX_12 [1:0] 1b = 64 mA
7	EN_DCC	R/W	0h	Enable duty cycle compensation for half-bridge 1 and 2.
6	IDIR_MAN	R/W	0h	Current polarity detection mode for half-bridge 1 and 2. 0b = Automatic 1b = Manual (Set by HBx_HL)
5-4	KP_PST	R/W	0h	Post charge proportional control gain setting for half-bridges 1 and 2. 00b = Disabled 01b = 2 10b = 4 11b = 15
3	EN_PST_DLY	R/W	0h	Enable post-charge time delay. Time delay is equal to T_DON_DOFF_12 - T_PRE_CHR_12.
2-1	KP_PDR	R/W	1h	PDR proportional controller gain setting for half-bridge 1 and 2. 00b = 1 01b = 2 10b = 3 11b = 4
0	EN_PDR	R/W	0h	Enable PDR loop control for half-bridge 1 and 2.

10.9 GD_PDR_CNFG Register (Offset = 11h) [Reset = 0AF6h]

GD_PDR_CNFG is shown in Table 10-11.

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Includes remaining PDR controls, pre-charge settings and timing.

Table 10-11 GD_PDR_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	PRE_MAX	R/W	0h	Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 1 and 2. 00b = 64 mA 01b = 32 mA 10b = 16 mA 11b = 8 mA
13-8	T_DON_DOFF	R/W	Ah	On and off time delay for half-bridge 1 and 2. 140 ns x T_DON_DOFF [3:0] Default time: 001010b (1.4 us)
7-6	T_PRE_CHR	R/W	3h	PDR control loop pre-charge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0] 00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2
5-4	T_PRE_DCHR	R/W	3h	PDR control loop pre-discharge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0] 00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2
3-2	PRE_CHR_INIT	R/W	1h	PDR control loop initial pre-charge current setting for half-bridge 1 and 2. 00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA
1-0	PRE_DCHR_INIT	R/W	2h	PDR control loop initial pre-discharge current setting for half-bridge 1 and 2. 00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA

10.10 GD_STC_CNFG Register (Offset = 12h) [Reset = 0026h]

GD_STC_CNFG is shown in Table 10-12.

Return to the Summary Table.

Includes configurations and enable for slew time control.

Table 10-12 GD_STC_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7-4	T_RISE_FALL	R/W	2h	Set switch-node VSH rise and fall time for half-bridge 1 and 2. 0000b = 0.35 us 0001b = 0.56 us 0010b = 0.77 us 0011b = 0.98 us 0100b = 1.33 us 0101b = 1.68 us 0110b = 2.03 us 0111b = 2.45 us 1000b = 2.94 us 1001b = 3.99 us 1010b = 4.97 us 1011b = 5.95 us 1100b = 7.98 us 1101b = 9.94 us 1110b = 11.97 us 1111b = 15.96 us
3	STC_ERR	R/W	0h	STC loop error limit for half-bridge 1 and 2 0b = 1-bit error 1b = Actual error
2-1	KP_STC	R/W	3h	STC proportional controller gain setting for half-bridge 1 and 2. 00b = 1 01b = 2 10b = 3 11b = 4
0	EN_STC	R/W	0h	Enable STC loop control for half-bridge 1 and 2.

10.11 GD_SPARE_CNFG1 Register (Offset = 13h) [Reset = 0000h]

GD_SPARE_CNFG1 is shown in Table 10-13.

Return to the Summary Table.

Spare configuration register for gate driver.

Table 10-13 GD_SPARE_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

10.12 HB_ITRIP_DG Register (Offset = 14h) [Reset = 0000h]

HB_ITRIP_DG is shown in Table 10-14.

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Configures ITRIP deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 10-14 HB_ITRIP_DG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-10	OUT6_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 6. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
9-8	OUT5_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 5. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
7-6	OUT4_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 4. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
5-4	OUT3_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 3. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
3-2	OUT2_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 2. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs
1-0	OUT1_ITRIP_DG	R/W	0h	Configures ITRIP deglitch time for half-bridge 1. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs

10.13 HB_OUT_CNFG1 Register (Offset = 15h) [Reset = 0000h]

HB_OUT_CNFG1 is shown in Table 10-15.

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Configures the output mode for each half-bridge, sets IPROPI sample and hold circuit, and half-bridge pair freewheeling.

Table 10-15 HB_OUT_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD	R/W	0h	Reserved.
14	NSR_OUT6_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 6. Passive freewheeling = 0b Active freewheeling = 1b
13	NSR_OUT5_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 5. Passive freewheeling = 0b Active freewheeling = 1b
12	NSR_OUT4_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 4. Passive freewheeling = 0b Active freewheeling = 1b
11	NSR_OUT3_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridges 3. Passive freewheeling = 0b Active freewheeling = 1b
10	NSR_OUT2_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 2. Passive freewheeling = 0b Active freewheeling = 1b
9	NSR_OUT1_DIS	R/W	0h	Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 1. Passive freewheeling = 0b Active freewheeling = 1b
8	IPROPI_SH_EN	R/W	0h	Enables IPROPI sample and hold circuit.
7	RSVD_7	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5-3	OUT6_CNFG	R/W	0h	Configuration for half-bridge 6. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control
2-0	OUT5_CNFG	R/W	0h	Configuration for half-bridge 5. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control

10.14 HB_OUT_CNFG2 Register (Offset = 16h) [Reset = 0000h]

HB_OUT_CNFG2 is shown in Table 10-16.

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Configures the output mode for each half-bridge.

Table 10-16 HB_OUT_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13-11	OUT4_CNFG	R/W	0h	Configuration for half-bridge 4. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control
10-8	OUT3_CNFG	R/W	0h	Configuration for half-bridge 3. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control
7	RSVD_7	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5-3	OUT2_CNFG	R/W	0h	Configuration for half-bridge 2. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control
2-0	OUT1_CNFG	R/W	0h	Configuration for half-bridge 1. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 PWM LS Control 111b = PWM2 HS Control

10.15 HB_OCP_CNFG Register (Offset = 17h) [Reset = 0000h]

HB_OCP_CNFG is shown in Table 10-17.

Return to the Summary Table.

Overcurrent deglitch for half-bridges configuration register.

Table 10-17 HB_OCP_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD	R/W	0h	Reserved.
14	RSVD	R/W	0h	Reserved.
13	RSVD	R/W	0h	Reserved.
12	RSVD	R/W	0h	Reserved.
11-10	OUT6_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 6. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
9-8	OUT5_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 5. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
7-6	OUT4_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 4. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
5-4	OUT3_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 3. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
3-2	OUT2_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 2. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
1-0	OUT1_OCP_DG	R/W	0h	Overcurrent deglitch time for half-bridge 1. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs

10.16 HB_OL_CNFG1 Register (Offset = 18h) [Reset = 0000h]

HB_OL_CNFG1 is shown in Table 10-18.

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Configures active and off-state open load detection circuits for half-bridges.

Table 10-18 HB_OL_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13-12	HB_OLP_CNFG	R/W	0h	Off-state diagnostics configuration. 00b = Off-state disabled 01b = OUT X Pull-up enabled, OUT Y pull-down enabled, OUT Y selected, VREF Low 10b = OUT X Pull-up enabled, OUT Y pull-down enabled, OUT X selected, VREF High 11b = OUT X Pull-down enabled, OUT Y pull-up enabled, OUT Y selected, VREF Low
11-8	HB_OLP_SEL	R/W	0h	Off-state open load diagnostics enable for half-bridge 5. 0000b = Disabled 0001b = OUT1 and OUT2 0010b = OUT1 and OUT3 0011b = OUT1 and OUT4 0100b = OUT1 and OUT5 0101b = OUT1 and OUT6 0110b = OUT2 and OUT3 0111b = OUT2 and OUT4 1000b = OUT2 and OUT5 1001b = OUT2 and OUT6 1010b = OUT3 and OUT4 1011b = OUT3 and OUT5 1100b = OUT3 and OUT6 1101b = OUT4 and OUT5 1110b = OUT4 and OUT6 1111b = OUT5 and OUT6
7	RSVD_7	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5	OUT6_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 6. 0b = Enabled 1b = Disabled
4	OUT5_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 5. 0b = Enabled 1b = Disabled
3	OUT4_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 4. 0b = Enabled 1b = Disabled
2	OUT3_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 3. 0b = Enabled 1b = Disabled
1	OUT2_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 2. 0b = Enabled 1b = Disabled
0	OUT1_OLA_EN	R/W	0h	Active open load diagnostics enable for half-bridge 1. 0b = Enabled 1b = Disabled

10.17 HB_OL_CNFG2 Register (Offset = 19h) [Reset = 0000h]

HB_OL_CNFG2 is shown in Table 10-19.

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Configures cycle count threshold for active open load detection circuits of half-bridges.

Table 10-19 HB_OL_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13	RSVD_13	R/W	0h	Reserved.
12	RSVD_12	R/W	0h	Reserved.
11	RSVD_11	R/W	0h	Reserved.
10	RSVD_10	R/W	0h	Reserved.
9	RSVD_9	R/W	0h	Reserved.
8	RSVD_8	R/W	0h	Reserved.
7	RSVD_7	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5	OUT6_OLA_TH	R/W	0h	Sets the half-bridge 6 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles
4	OUT5_OLA_TH	R/W	0h	Sets the half-bridge 5 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles
3	OUT4_OLA_TH	R/W	0h	Sets the half-bridge 4 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles
2	OUT3_OLA_TH	R/W	0h	Sets the half-bridge 3 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles
1	OUT2_OLA_TH	R/W	0h	Sets the half-bridge 2 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles
0	OUT1_OLA_TH	R/W	0h	Sets the half-bridge 1 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles

10.18 HB_SR_CNFG Register (Offset = 1Ah) [Reset = 0000h]

HB_SR_CNFG is shown in Table 10-20.

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Configures slew rate timing for each half-bridge.

Table 10-20 HB_SR_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13	RSVD_13	R/W	0h	Reserved.
12	RSVD_12	R/W	0h	Reserved.
11-10	OUT6_SR	R/W	0h	Configures slew rate for half-bridge 6. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs
9-8	OUT5_SR	R/W	0h	Configures slew rate for half-bridge 5. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs
7-6	OUT4_SR	R/W	0h	Configures slew rate for half-bridge 4. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs
5-4	OUT3_SR	R/W	0h	Configures slew rate for half-bridge 3. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs
3-2	OUT2_SR	R/W	0h	Configures slew rate for half-bridge 2. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs
1-0	OUT1_SR	R/W	0h	Configures slew rate for half-bridge 1. 00b = 1.6 V/µs 01b = 10 V/µs 10b = 20 V/µs

10.19 HB_ITRIP_CNFG Register (Offset = 1Bh) [Reset = 0000h]

HB_ITRIP_CNFG is shown in Table 10-21.

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Configures ITRIP levels and enables ITRIP for each half-bridge. ITRIP levels are shared between half-bridge pairs.

Table 10-21 HB_ITRIP_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	OUT6_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 6.
14	OUT5_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 5.
13	OUT4_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 4.
12	OUT3_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 3.
11	OUT2_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 2.
10	OUT1_ITRIP_EN	R/W	0h	Enables ITRIP regulation for half-bridge 1.
9-8	OUT6_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 6. 00b = 2.25 A 01b = 5.5 A 10b = 6.25 A 11b = Reserved.
7-6	OUT5_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 5. 00b = 2.75 A 01b = 6.5 A 10b = 7.5 A 11b = Reserved.
5-4	OUT4_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 4. 00b = 1.25 A 01b = 2.75 A 10b = 3.5 A 11b = Reserved.
3-2	OUT3_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 3. 00b = 1.25 A 01b = 2.5 A 10b = 3.5 A 11b = Reserved.
1	OUT2_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 2. 0b = 0.7 A 1b = 0.875 A
0	OUT1_ITRIP_LVL	R/W	0h	Configures ITRIP current threshold for half-bridge 1. 0b = 0.7 A 1b = 0.875 A

10.20 HB_ITRIP_FREQ Register (Offset = 1Ch) [Reset = 0000h]

HB_ITRIP_FREQ is shown in Table 10-22.

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Configures ITRIP frequency and deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 10-22 HB_ITRIP_FREQ Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13	RSVD_13	R/W	0h	Reserved.
12	RSVD_12	R/W	0h	Reserved.
11-10	OUT6_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 6. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
9-8	OUT5_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 5. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
7-6	OUT4_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 4. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
5-4	OUT3_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 3. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
3-2	OUT2_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 2. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz
1-0	OUT1_ITRIP_FREQ	R/W	0h	Configures ITRIP regulation frequency for half-bridge 1. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz

10.21 HS_HEAT_OUT_CNFG Register (Offset = 1Dh) [Reset = 0000h]

HS_HEAT_OUT_CNFG is shown in Table 10-23.

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Configures the output mode for each high-side driver and heater.

Table 10-23 HS_HEAT_OUT_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	HEAT_OUT_CNFG	R/W	0h	Configuration for heater driver. Enables or disables control of heater, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = Reserved
13	RSVD_13	R/W	0h	Reserved.
12	RSVD_12	R/W	0h	Reserved.
11-10	OUT12_CNFG	R/W	0h	Configuration for high-side driver 12. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
9-8	OUT11_CNFG	R/W	0h	Configuration for high-side driver 11. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
7-6	OUT10_CNFG	R/W	0h	Configuration for high-side driver 10. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
5-4	OUT9_CNFG	R/W	0h	Configuration for high-side driver 9. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
3-2	OUT8_CNFG	R/W	0h	Configuration for high-side driver 8. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator
1-0	OUT7_CNFG	R/W	0h	Configuration for high-side driver 7. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator

10.22 HS_OC_CNFG Register (Offset = 1Eh) [Reset = 1000h]

HS_OC_CNFG is shown in Table 10-24.

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Configures overcurrent threshold for each high-side driver.

Table 10-24 HS_OC_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13	RSVD_13	R/W	0h	Reserved.
12	OUT11_EC_MODE	R/W	1h	Bit sets high-side OUT11 for independent control through OUT11_CNFG bits or for EC mode. Default configuration is for EC mode. OUT11_CNFG mode = 0b EC mode = 1b
11	RSVD_12	R/W	0h	Reserved.
10	RSVD_11	R/W	0h	Reserved.
9	RSVD_10	R/W	0h	Reserved.
8	RSVD_9	R/W	0h	Reserved.
7	RSVD_8	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5	OUT12_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 12. 0b = Low current threshold 1b = High current threshold
4	OUT11_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 11. 0b = Low current threshold 1b = High current threshold
3	OUT10_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 10. 0b = Low current threshold 1b = High current threshold
2	OUT9_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 9. 0b = Low current threshold 1b = High current threshold
1	OUT8_OC_TH	R/W	0h	Configures overcurrent threshold between high or low for high-side driver 8. 0b = Low current threshold 1b = High current threshold
0	OUT7_RDSON_MODE	R/W	0h	Configures high-side driver 7 between high RDSON mode and low RDSON mode (for bulb/lamp load). 0b = High RDSON mode (LED driver mode) 1b = Low RDSON mode (bulb/lamp driver mode)

10.23 HS_OL_CNFG Register (Offset = 1Fh) [Reset = 0000h]

HS_OL_CNFG is shown in Table 10-25.

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Configures open load threshold for each high-side driver.

Table 10-25 HS_OL_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RSVD_15	R/W	0h	Reserved.
14	RSVD_14	R/W	0h	Reserved.
13	OUT12_OLA_TH	R/W	0h	Configures high-side driver 12 open load threshold. 0b = Low threshold 1b = High threshold
12	OUT11_OLA_TH	R/W	0h	Configures high-side driver 11 open load threshold. 0b = Low threshold 1b = High threshold
11	OUT10_OLA_TH	R/W	0h	Configures high-side driver 10 open load threshold. 0b = Low threshold 1b = High threshold
10	OUT9_OLA_TH	R/W	0h	Configures high-side driver 9 open load threshold. 0b = Low threshold 1b = High threshold
9	OUT8_OLA_TH	R/W	0h	Configures high-side driver 8 open load threshold. 0b = Low threshold 1b = High threshold
8	OUT7_OLA_TH	R/W	0h	Configures high-side driver 7 open load threshold. 0b = Low threshold 1b = High threshold
7	RSVD_7	R/W	0h	Reserved.
6	RSVD_6	R/W	0h	Reserved.
5	OUT12_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 12.
4	OUT11_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 11.
3	OUT10_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 10.
2	OUT9_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 9.
1	OUT8_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 8.
0	OUT7_OLA_EN	R/W	0h	Enables open load detection circuit for high-side driver 7.

10.24 HS_REG_CNFG1 Register (Offset = 20h) [Reset = 0000h]

HS_REG_CNFG1 is shown in Table 10-26.

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Configures OUT7 ITRIP settings.

Table 10-26 HS_REG_CNFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	OUT7_OCP_DIS	R/W	0h	Disables second current limit of 2.5A on OUT7 in low RDSON mode. 0b = OUT7 OCP enable 1b = OUT7 OCP disable
9-8	ITRIP_TO_SEL	R/W	0h	Selects the timeout limit for OUT7 ITRIP regulation. 00b = 100 ms 01b = 200 ms 10b = 400 ms 11b = 800 ms
7-6	OUT7_ITRIP_CNFG	R/W	0h	Configures OUT7 ITRIP behavior, fault clearing and latching. 00b = ITRIP fault report only 01b = ITRIP regulation with timeout and driver disable 10b = ITRIP regulation always 11b = ITRIP regulation with timeout and regulation disable
5-4	OUT7_ITRIP_BLK	R/W	0h	Configures OUT7 ITRIP blanking time. 00b = Reserved. 01b = 0 µs 10b = 20 µs 11b = 40 µs
3-2	OUT7_ITRIP_FREQ	R/W	0h	Configures OUT7 ITRIP regulation frequency. 00b = 1.7 kHz 01b = 2.2 kHz 10b = 3 kHz 11b = 4.4 kHz
1-0	OUT7_ITRIP_DG	R/W	0h	Configures OUT7 ITRIP deglitch time. 00b = 48 µs 01b = 40 µs 10b = 32 µs 11b = 24 µs

10.25 HS_REG_CNFG2 Register (Offset = 21h) [Reset = 0000h]

HS_REG_CNFG2 is shown in Table 10-27.

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Configures constant current mode for each high-side driver.

Table 10-27 HS_REG_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	OUT12_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 12. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
12	OUT11_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 11. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
11	OUT10_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 10. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
10	OUT9_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 9. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
9	OUT8_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 8. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
8	OUT7_CCM_TO	R/W	0h	Configures the constant current mode timing and current limit option of high-side output 7. 200 mA for 20 ms = 0b 390 mA for 10 ms = 1b
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	OUT12_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 12.
4	OUT11_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 11.
3	OUT10_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 10.
2	OUT9_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 9.
1	OUT8_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 8.
0	OUT7_CCM_EN	R/W	0h	Enables constant current mode circuit for high-side driver 7.

10.26 HS_PWM_FREQ_CNFG Register (Offset = 22h) [Reset = 0000h]

HS_PWM_FREQ_CNFG is shown in Table 10-28.

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Configures the frequency for each dedicated PWM generator.

Table 10-28 HS_PWM_FREQ_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-10	PWM_OUT12_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 12. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved
9-8	PWM_OUT11_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 11. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved
7-6	PWM_OUT10_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 10. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved
5-4	PWM_OUT9_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 9. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved
3-2	PWM_OUT8_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 8. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved
1-0	PWM_OUT7_FREQ	R/W	0h	Configures frequency output of dedicated PWM generator for high-side driver 7. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = Reserved

10.27 HEAT_CNFG Register (Offset = 23h) [Reset = 0A3Ch]

HEAT_CNFG is shown in Table 10-29.

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Configures heater driver and fault responses.

Table 10-29 HEAT_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-8	HEAT_VDS_LVL	R/W	Ah	Heater MOSFET VDS monitor protection threshold. 0000b = 0.06 V 00001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.24 V 1001b = 0.28 V 1010b = 0.32 V 1011b = 0.36 V 1100b = 0.4 V 1101b = 0.44 V 1110b = 0.56 V 1111b = 1 V
7-6	HEAT_VDS_MODE	R/W	0h	Heater MOSFET VDS overcurrent monitor fault mode. 00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled.
5-4	HEAT_VDS_BLK	R/W	3h	Heater MOSFET VDS monitor blanking time. 00b = 4 µs 01b = 8 µs 10b = 16 µs 11b = 32 µs
3-2	HEAT_VDS_DG	R/W	3h	Heater MOSFET VDS overcurrent monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs
1	HEAT_OLP_EN	R/W	0h	Enables heater offline open load detection circuit.
0	RESERVED	R	0h	Reserved

10.28 EC_CNFG Register (Offset = 24h) [Reset = 0000h]

EC_CNFG is shown in Table 10-30.

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Configures electrochrome driver and fault responses.

Table 10-30 EC_CNFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ECDRV_OL_EN	R/W	0h	When the EC driver is in PVDD Supply/OUT11 Independent EC Mode (OUT11_EC_MODE = 0b), this bit enables the current source for open-load detection on ECFB. This bit can be ignored if the default configuration of EC is used (OUT11_EC_MODE = 1b). 0b = EC Open-load current source disabled 1b = EC Open-load current source enabled
14	ECFB_UV_TH	R/W	0h	Sets the ECFB undervoltage (short to ground) threshold. 0b = 100 mV 1b = 200 mV
13	RSVD_13	R/W	0h	Reserved.
12	RSVD_12	R/W	0h	Reserved.
11-10	ECFB_UV_DG	R/W	0h	Configures undervoltage fault deglitch time. 00b = 20 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs
9-8	ECFB_OV_DG	R/W	0h	Configures overvoltage fault deglitch time. 00b = 20 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs
7-6	ECFB_UV_MODE	R/W	0h	Configures ECFB UV fault response for EC driver. 0b = No action 01b = Report ECFB voltage < ECFB_UV_TH 10b = Report ECFB voltage < ECFB_UV_TH and disable EC driver.
5-4	ECFB_OV_MODE	R/W	0h	Configures ECFB OV fault response for EC driver. 0b = No action 01b = Report ECFB voltage < ECFB_OV_TH 10b = Report ECFB voltage < ECFB_OV_TH and disable EC driver.
3	EC_FLT_MODE	R/W	0h	Configures overcurrent fault response for EC driver. 0b = Hi-Z EC Driver 1b = Retry with OUT7 ITRIP settings
2	ECFB_LS_PWM	R/W	0h	Enables LS PWM discharge for EC load. 0b = No PWM discharge (Fast discharge) 1b = PWM discharge enabled
1	EC_OLEN	R/W	0h	This bit enables the open load detection circuit during EC discharge. 0b = Open load detection disabled during EC discharge 1b = Open load detection enabled during EC discharge
0	ECFB_MAX	R/W	0h	Configures the maximum target voltage for EC. 0b = 1.2 V 1b = 1.5 V

10.29 HS_OCP_DG Register (Offset = 25h) [Reset = 0000h]

HS_OCP_DG is shown in Table 10-31.

Return to the Summary Table.

High-side driver overcurrent deglitch configuration reguration register.

Table 10-31 HS_OCP_DG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11-10	OUT12_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 12. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
9-8	OUT11_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 11. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
7-6	OUT10_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 10. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
5-4	OUT9_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 9. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
3-2	OUT8_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 8. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs
1-0	OUT7_OCP_DG	R/W	0h	Overcurrent deglitch time for high-side driver 7. 00b = 6 µs 01b = 10 µs 10b = 20 µs 11b = 60 µs

10.30 SPARE_CNFG2 Register (Offset = 26h) [Reset = 0000h]

SPARE_CNFG2 is shown in Table 10-32.

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Spare configuration 2.

Table 10-32 SPARE_CNFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

10.31 SPARE_CNFG3 Register (Offset = 27h) [Reset = 0000h]

SPARE_CNFG3 is shown in Table 10-33.

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Spare configuration 3.

Table 10-33 SPARE_CNFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

10.32 SPARE_CNFG4 Register (Offset = 28h) [Reset = 0000h]

SPARE_CNFG4 is shown in Table 10-34.

Return to the Summary Table.

Spare configuration 4.

Table 10-34 SPARE_CNFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved