An SPI bus is used to set device configurations, operating parameters, and read out diagnostic information on the DRV8000-Q1 device. The SPI operates in slave mode and connects to a master controller. The SPI input data (SDI) word consists of a 24 bit word, with an 8 bit command and 16 bits of data. The SPI output data (SDO) word for read commands consists of the fault status indication bits and then the register data being accessed for read commands. The SDO word for write commands consists of the command data followed by the existing data in the register being written to. The data sequence between the MCU and the SPI slave driver is shown in Figure 7-36.

Figure 7-36 SPI Data Frame

A valid frame must meet the following conditions:

• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 24 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 24 bits, a frame error (SCLK_FLT) occurs and the data word is ignored.
• For a write command, following the 16-bit command data, the existing data in the register being written to is shifted out on the SDO pin starting with fault status byte then 16-bit data .

Figure 7-37 SPI Slave Timing Diagram