SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DRV8000-Q1 VQFN (RGZ) 48-Pin Package and Pin Functions Figure 5-1 VQFN (RGZ) 48-Pin Package and Pin Functions
Table 5-1 Pin Functions
PIN I/O(1) TYPE DESCRIPTION
NO. NAME

1

 OUT4 O Power 400mΩ half-bridge output 4.
2 PVDD I Power Device driver power supply input. Connect to the bridge power supply. Connect a 0.1μF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10μF between PVDD and GND pins.
3 VCP I/O Power Charge pump output. Connect a 1μF, 16V ceramic capacitor between VCP and PVDD pins.
4 CP1H I/O Power Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CP1H and CP1L pins.
5 CP1L I/O Power
6 CP2H I/O Power Charge pump switching node. Connect a 100nF, PVDD-rated ceramic capacitor between the CP2H and CP2L pins.
7 CP2L I/O Power

8

 PVDD I Power Device driver power supply input. Connect to the bridge power supply. Connect a 0.1µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10µF between PVDD and GND pins.

9

 OUT5 O Power 132mΩ half-bridge output 5.

10

 PGND I/O Ground Device ground. Connect to system ground.

11

 OUT1 O Power 1.5Ω half-bridge output 1.

12

 OUT2 O Power 1.5Ω half-bridge output 2.

13

 GD_IN1 I Digital Half-bridge and H-bridge control input 1.

14

GD_IN2

I

Digital

 Half-bridge and H-bridge control input 2.
15 PWM1 I Digital PWM input 1 for regulation of all drivers except electrochrome.
16 nSCS I Digital Serial chip select. A logic low on this pin enables serial interface communication. Internal pull-up resistor.
17 SDI I Digital Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pull-down resistor.
18 SDO O Digital Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output.
19 SCLK I Digital Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pull-down resistor.

20

 IPROPI/PWM2 I/O Analog Sense output is multiplexed from any of driver load current feedback, PVDD voltage feedback, or thermal cluster temperature feedback. Can also be configured as second PWM pin input for half-bridge drivers.
21 SO O Analog Shunt amplifier output.
22 DRVOFF I Analog Gate driver shutdown pin. Logic high to pull down both high-side and low-side gate driver outputs. Internal pull-down resistor.

23

 nSLEEP I Analog Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pull-down resistor.

24

 DVDD I Power Device logic and digital output power supply input. Recommended to connect a 1.0µF, 6.3V ceramic capacitor between the DVDD and GND pins.

25

 DGND I/O Ground Device ground. Connect to system ground.

26

 ECFB I/O Power For EC control, pin is used as voltage monitor input and fast discharge low-side switch. If the EC drive function is not used, connect this pin to GND through 10kΩ resistor.

27

 ECDRV O Analog For EC control, pin controls the gate of external MOSFET for EC voltage regulation
28 SH_HS I Analog Source pin of high-side heater MOSFET and output to heater load. Connect to source of high-side MOSFET.
29 GH_HS O Analog Gate driver output for heater MOSFET. Connect to gate of high-side MOSFET.
30 SN I Analog Amplifier negative input. Connect to negative terminal of the shunt resistor.
31 SP I Analog Amplifier positive input. Connect to positive terminal of the shunt resistor.
32 GH2 O Analog High-side gate driver output. Connect to the gate of the high-side MOSFET.
33 SH2 I Analog High-side source sense input. Connect to the high-side MOSFET source.
34 GL2 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
35 SL I Analog Low-side MOSFET gate drive sense and power return. Connect to system ground with low impedance path to the low-side MOSFET ground return.
36 GL1 O Analog Low-side gate driver output. Connect to the gate of the low-side MOSFET.
37 SH1 I Analog High-side source sense input. Connect to the high-side MOSFET source.
38 GH1 O Power High-side gate driver output. Connect to the gate of the high-side MOSFET.

39

 OUT12 O Power 1.5Ω high-side driver output 12. Connect to low-side load.

40

 OUT11 O Power 1.5Ω high-side driver output 11. Configurable as SC protection switch for EC drive. Connect to low-side load.

41

 OUT10 O Power 1.5Ω high-side driver output 10. Connect to low-side load.

42

 OUT9 O Power 1.5-Ω high-side driver output 9. Connect to low-side load.

43

 OUT8 O Power 1.5-Ω high-side driver output 8. Connect to low-side load.

44

 OUT7 O Power High-side driver output with configurable RDSON (400mΩ/1500mΩ). Connect to low-side load.

45

 PVDD I Power Device driver power supply input. Connect to the bridge power supply. Connect a 0.1µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10µF between PVDD and GND pins.

46

 OUT6 O Power 160mΩ half-bridge output 6.

47

 PGND I/O Ground Device ground. Connect to system ground.

48

 OUT3 O Power 400mΩ half-bridge output 3.
(1) I = Input, O = Output
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