ZHCSQH2 July   2024 DRV81008-Q1

ADVANCE INFORMATION  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active mode
          5. 7.3.2.1.5 Limp Home mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Switching Channels in parallel
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Input 0 Mapping Register
          4. 7.3.5.4.4  Input 1 Mapping Register
          5. 7.3.5.4.5  Input Status Monitor Register
          6. 7.3.5.4.6  Open Load Current Control Register
          7. 7.3.5.4.7  Output Status Monitor Register
          8. 7.3.5.4.8  Configuration Register
          9. 7.3.5.4.9  Output Clear Latch Register
          10. 7.3.5.4.10 Configuration Register 2
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Suggested External Components
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
  10. Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

  • The VM pin should be bypassed to GND using low-ESR ceramic bypass capacitor with a recommended value of 68nF rated for VM. The capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin.

  • Bypass the VDD pin to ground with a low-ESR ceramic capacitor. A value of 100nF rated for 6.3V is recommended. Place this bypassing capacitor as close to the pin as possible.

  • In general, inductance between the power supply pins and decoupling capacitors must be avoided.

  • Connect series resistors between IN0, IN1, nSLEEP, nSCS, SCLK, SDI, SDO and VDD pins of the DRV81008-Q1 and corresponding pins of the microcontroller. The recommended values of the resistors are shown in Section 7.3.

  • The thermal PAD of the package must be connected to system ground.

    • It is recommended to use a big unbroken single ground plane for the whole system / board. The ground plane can be made at bottom PCB layer.

    • In order to minimize the impedance and inductance, the traces from ground pins should be as short and wide as possible, before connecting to bottom layer ground plane through vias.

    • Multiple vias are suggested to reduce the impedance.

    • Try to clear the space around the device as much as possible especially at bottom PCB layer to improve the heat spreading.

    • Single or multiple internal ground planes connected to the thermal PAD will also help spreading the heat and reduce the thermal resistance.