ZHCSQH2 July   2024 DRV81008-Q1

ADVANCE INFORMATION  

1.   1
2. 1 特性
3. 2 应用
4. 3 说明
5. 4 Revision History
6. 5 Pin Configuration and Functions
7. 6 Specifications
   1. 6.1 Absolute Maximum Ratings
   2. 6.2 ESD Ratings
   3. 6.3 Recommended Operating Conditions
   4. 6.4 Thermal Information
   5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
8. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Control Pins
         1. 7.3.1.1 Input Pins
         2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
         1. 7.3.2.1 Modes of Operation
            1. 7.3.2.1.1 Power-up
            2. 7.3.2.1.2 Sleep mode
            3. 7.3.2.1.3 Idle mode
            4. 7.3.2.1.4 Active mode
            5. 7.3.2.1.5 Limp Home mode
         2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
         1. 7.3.3.1 Switching Resistive Loads
         2. 7.3.3.2 Inductive Output Clamp
         3. 7.3.3.3 Maximum Load Inductance
         4. 7.3.3.4 Switching Channels in parallel
      4. 7.3.4 Protection and Diagnostics
         1. 7.3.4.1 Undervoltage on VM
         2. 7.3.4.2 Overcurrent Protection
         3. 7.3.4.3 Over Temperature Protection
         4. 7.3.4.4 Over Temperature Warning
         5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
         6. 7.3.4.6 Reverse Polarity Protection
         7. 7.3.4.7 Over Voltage Protection
         8. 7.3.4.8 Output Status Monitor
      5. 7.3.5 SPI Communication
         1. 7.3.5.1 SPI Signal Description
            1. 7.3.5.1.1 Chip Select (nSCS)
               1. 7.3.5.1.1.1 Logic high to logic low Transition
               2. 7.3.5.1.1.2 Logic low to logic high Transition
            2. 7.3.5.1.2 Serial Clock (SCLK)
            3. 7.3.5.1.3 Serial Input (SDI)
            4. 7.3.5.1.4 Serial Output (SDO)
         2. 7.3.5.2 Daisy Chain Capability
         3. 7.3.5.3 SPI Protocol
         4. 7.3.5.4 SPI Registers
            1. 7.3.5.4.1  Standard Diagnosis Register
            2. 7.3.5.4.2  Output control register
            3. 7.3.5.4.3  Input 0 Mapping Register
            4. 7.3.5.4.4  Input 1 Mapping Register
            5. 7.3.5.4.5  Input Status Monitor Register
            6. 7.3.5.4.6  Open Load Current Control Register
            7. 7.3.5.4.7  Output Status Monitor Register
            8. 7.3.5.4.8  Configuration Register
            9. 7.3.5.4.9  Output Clear Latch Register
            10. 7.3.5.4.10 Configuration Register 2
9. 8 Application and Implementation
   1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Suggested External Components
   2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
11. 10Mechanical, Packaging, and Orderable Information
12. 11Mechanical, Packaging, and Orderable Information