ZHCSQH2 July   2024 DRV81008-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active mode
          5. 7.3.2.1.5 Limp Home mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Switching Channels in parallel
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Input 0 Mapping Register
          4. 7.3.5.4.4  Input 1 Mapping Register
          5. 7.3.5.4.5  Input Status Monitor Register
          6. 7.3.5.4.6  Open Load Current Control Register
          7. 7.3.5.4.7  Output Status Monitor Register
          8. 7.3.5.4.8  Configuration Register
          9. 7.3.5.4.9  Output Clear Latch Register
          10. 7.3.5.4.10 Configuration Register 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Suggested External Components
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

VDD = 3 V to 5.5 V, VM = 4 V to 40 V, TJ = -40 °C to +150 °C (unless otherwise noted)

Typical values: VDD = 5 V, VM = 13.5 V, TJ = 25 °C

PARAMETERTEST CONDITIONSMINTYPMAXUNIT

POWER SUPPLY (VM, VDD)

VM_OP

VM minimum operating voltage

ENx = 1b, from UVRVM = 1b to VDS ≤ 1 V, RL = 50 Ω

4

V

VDD_OPVDD Operating voltagefSCLK = 5 MHz

3

5.5

V

VMDIFF

Voltage difference between VM and VDD

210

mV

IVM_SLEEP

Analog supply current in sleep mode

nSLEEP, IN0, IN1 floating, nSCS = VDDTJ ≤ 85 °C

1.2

2.5

μA

TJ = 150 °C

1.4

3

μA

IVDD_SLEEP

Logic supply current in sleep modenSLEEP, IN0, IN1 floating, nSCS = VDDTJ ≤ 85 °C

0.4

0.8

μA
TJ = 150 °C

5

μA

ISLEEP

Overall current consumption in Sleep modenSLEEP, IN0, IN1 floating, nSCS = VDDTJ ≤ 85 °C

3.5

μA
TJ = 150 °C

8

μA

IVM_IDLE

Analog supply current in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, IOLx = 0b, nSCS = VDD

1.75

mA

COR mode, VM ≤ VDD - 1 V

0.25

mA

IVDD_IDLELogic supply current in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, nSCS = VDD

0.5

mA

COR mode, VM ≤ VDD - 1 V

1.5

mA
IIDLEOverall current consumption in Idle modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 0b, ENx = 0b, IOLx = 0b, nSCS = VDD

2

mA

IVM_ACT

Analog supply current in Active modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, IOLx = 0b, nSCS = VDD

3

mA

COR mode, VM ≤ VDD - 1 V

0.1

0.2

mA

IVDD_ACTLogic supply current in Active modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, nSCS = VDD

0.5

mA

COR mode, VM ≤ VDD - 1 V

2.7

mA

IACTOverall current consumption in Active modenSLEEP = logic high, IN0, IN1 floating, fSCLK = 0 MHz, ACT = 1b, IOLx = 0b, nSCS = VDD

3.2

mA

tS2I

Sleep to Idle delay

240

300

μs

tI2S

Idle to Sleep delay

100

150

μs

tI2A

Idle to Active delay

100

150

μs

tA2I

Active to Idle delay

100

150

μs

tS2LH

Sleep to Limp Home delay

350 + tON

450 + tONμs

tLH2S

Limp Home to Sleep delay

200 + tOFF250 + tOFF

μs

tLH2A

Limp Home to Active delay

50

100

μs

tA2LH

Active to Limp Home delay

52

100

μs

tA2S

Active to Sleep delay

50

100

μs

CONTROL AND SPI INPUTS (nSLEEP, IN0, IN1, nSCS, SCLK, SDI)

VIL

Input logic low voltage

0

0.8

V

VIH

Input logic high voltage (nSLEEP, IN0, IN1)

2

5.5

V

VIH_SPIInput logic high voltage (nSCS, SCLK, SDI)

2

VDD

V

IIL

Input logic low current (all pins except nSCS)

VI = 0.8 V

9

12

15

μA

IIL_nSCSnSCS input logic low currentVnSCS = 0.8 V, VDD = 5 V

25

60

75

μA

IIH

Input logic high current (all pins except nSCS)

VI = 2 V

20

30

40

μA

IIH_nSCS

nSCS input logic high currentVnSCS = 2 V, VDD = 5 V

10

42

55

μA

PUSH-PULL OUTPUT (SDO)

VSDO_L

Output logic low voltage

ISDO = -1.5 mA

0

0.4

V

VSDO_H

Output logic high voltage

ISDO = 1.5 mA

VDD - 0.4

VDD

V

ISDO_OFF

SDO tristate leakage current

VnSCS = VDD, VSDO = 0 V or VDD

-0.5

0.5

μA

POWER STAGE

RDS(ON)

ON resistance

TJ = 25 °C

0.63

0.85

Ω

TJ = 150 °C, IL = IL_EAR = 220 mA

0.95

1.3

IL_NOM

Nominal load current (all channels active)

TA = 85 °C, TJ ≤ 150 °C

330

500

mA

TA = 105 °C, TJ ≤ 150 °C

260

500

mA

IL_NOMNominal load current (half of the channels active)TA = 85 °C, TJ ≤ 150 °C

470

500

mA

IL_EAR

Load current for maximum energy dissipation - repetitive (all channels active)

TA = 85 °C, TJ ≤ 150 °C

220

mA

EAR

Maximum energy dissipation repetitive pulses- 2*IL_EAR (two channels in parallel)TJ(0) = 85 °C, IL(0) = 2*IL_EAR, 2*106 cycles, PAR = 1b for affected channels

15

mJ

VDS_OPPower stage voltage drop at low batteryRL = 50 Ω supplied by VM = 4 V

0.2

V

VDS_CLDrain to Source Output clamping voltageIL = 20 mA

44

46

48

V

IL_OFFOutput leakage current (each channel)VIN = 0 V or floating, VDS = 28 V, ENx = 0bTJ ≤ 85 °C

0.6

1.5

μA
TJ = 150 °C

1

6

μA
tDLY_ONTurn-ON delay (from INx pin or bit to VOUT = 90% VM)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

3

4

6

μs
tDLY_OFFTurn-OFF delay (from INx pin or bit to VOUT = 10% VM)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

6

8

11

μs
tONTurn-ON time (from INx pin or bit to VOUT = 10% VM)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

12

15

18

μs
tOFFTurn-OFF time (from INx pin or bit to VOUT = 90% VM)RL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

15

18

22

μs
tON - tOFFTurn-ON/OFF matchingRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

-10

0

10

μs
SRONTurn-ON slew rate, VDS = 70% to 30% VMRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

1

1.3

1.7

V/μs
SROFFTurn-OFF slew rate, VDS = 30% to 70% VMRL = 50 Ω, VM = 13.5 V, Active mode or Limp Home mode

1

1.3

1.7

V/μs
tSYNCInternal reference frequency synchronization time

5

10

μs

PROTECTION

VM_UVLO_FVM undervoltage shutdown (falling)ENx = ON, from VDS ≤ 1 V to UVRVM = 1b, RL = 50 Ω

2.6

2.73

2.86

V

VM_UVLO_RVM undervoltage shutdown (rising)

2.7

2.85

3

V

VDD_UVLOVDD undervoltage shutdown (rising)VSDI = VSCLK = VnSCS = 0 V, SDO from low to Hi-Z

2.55

2.7

2.85

V

VDD_HYS

VDD undervoltage shutdown hysteresis

100

120

140

mV

IL_OCP0

Overcurrent protection threshold, OCP = 0b

TJ = -40 °C

1.3

1.7

2

A

TJ = 25 °C

1.3

1.55

1.8

A

TJ = 150 °C

1.1

1.4

1.7

A

IL_OCP1Overcurrent protection threshold, OCP = 0bTJ = -40 °C

0.7

0.9

1.1

A

TJ = 25 °C

0.65

0.85

1.05

A

TJ = 150 °C

0.6

0.8

1

A

IL_OCP0Overcurrent protection threshold, OCP = 1bTJ = -40 °C

1.9

2.35

2.8

A
TJ = 25 °C

1.8

2.25

2.7

A
TJ = 150 °C

1.6

1.95

2.3

A
IL_OCP1Overcurrent protection threshold, OCP = 1bTJ = -40 °C

1.3

1.6

1.9

A
TJ = 25 °C

1.2

1.5

1.8

A
TJ = 150 °C

1.1

1.4

1.7

A
tOCPINOvercurrent threshold switch delay time

110

170

260

μs
tOFF_OCPOvercurrent shut-down delay time

4

7

11

μs

TOTW

Overtemperature warning

120

140

160

°C

THYS_OTW

Overtemperature warning

hysteresis

12

°C

TTSD

Thermal shut-down temperature

150

175

200

°C
VM_AZ

Over voltage protection

IVM = 10 mA, Sleep mode

46

48

50

V

VDS_REVDrain Source diode during reverse polarityIL = -10 mA, Sleep modeTJ = 25 °C

670

mV

TJ = 150 °C

530

mV

tRETRY0_LHRestart time in Limp Home mode

7

10

13

ms

tRETRY1_LHRestart time in Limp Home mode

14

20

26

ms

tRETRY2_LHRestart time in Limp Home mode

28

40

52

ms

tRETRY3_LHRestart time in Limp Home mode

56

80

104

ms

tOSMOutput Status Monitor comparator settling time

20

μs
VDS_OLOutput Status Monitor threshold voltage

2.9

3.3

3.7

V

IOLOutput diagnosis currentVDS = 3.3 V

15

75

85

μA
IOLOutput diagnosis currentVDS = 3.3 V, VM = 13.5 V

65

75

85

μA
ROLOpen Load equivalent resistance

110

190

kΩ
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