ZHCSQH2 July 2024 DRV81008-Q1
ADVANCE INFORMATION
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME |
NO. |
||
VM |
20 |
P |
Analog supply voltage for power stage and protection circuits |
VDD |
24 |
P |
Digital supply voltage for SPI |
GND |
5, 8, 17 |
G |
Ground pin |
nSCS |
1 |
I |
Serial chip select. An active low on this pin enables the serial interface communications. Integrated pull-up to VDD. |
SCLK |
2 |
I |
Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Integrated pull-down to GND. |
SDI |
3 |
I |
Serial data input. Data is captured on the falling edge of SCLK. Integrated pull-down to GND. |
SDO |
4 |
O |
Serial data output. Data is shifted out on the rising edge of SCLK. |
nSLEEP |
21 |
I |
Logic high activates Idle mode. Integrated pull-down to GND. |
IN0 |
23 |
I |
Connected to channel 2 by default and in Limp Home mode. Integrated pull-down to GND. |
IN1 |
22 |
I |
Connected to channel 3 by default and in Limp Home mode. Integrated pull-down to GND. |
OUT0 |
6 |
O |
Drain of low-side FET (channel 0) |
OUT2 |
7 |
O |
Drain of low-side FET (channel 2) |
OUT4 |
9 |
O |
Drain of low-side FET (channel 4) |
OUT6 |
12 |
O |
Drain of low-side FET (channel 6) |
OUT7 |
13 |
O |
Drain of low-side FET (channel 7) |
OUT5 |
16 |
O |
Drain of low-side FET (channel 5) |
OUT3 |
18 |
O |
Drain of low-side FET (channel 3) |
OUT1 |
19 |
O |
Drain of low-side FET (channel 1) |
NC |
10, 11, 14, 15 |
- |
No connect, internally not bonded |
PAD |
- |
- |
Exposed pad. Connect the exposed pad to PCB ground for cooling and EMC. |