ZHCSQH2 July 2024 DRV81008-Q1
ADVANCE INFORMATION
The DRV81008-Q1 is supplied by two supply voltages:
VM (analog supply voltage used also for the logic)
VDD (digital supply voltage)
The VM supply line is connected to a battery feed and used, in combination with VDD supply, for the driving circuitry of the power stages. In situations where VM voltage drops below VDD voltage (for example during cranking events down to 3 V), an increased current consumption may be observed at VDD pin. VM and VDD supply voltages have an undervoltage detection circuit.
An undervoltage on both VM and VDD supply voltages prevents the activation of the power stages and any SPI communication (the SPI registers are reset)
An undervoltage on VDD supply prevents any SPI communication. SPI read/write registers are reset to default values.
An undervoltage on VM supply forces the DRV81008-Q1 to drain all needed current for the low-side switches and for the logic from VDD supply.
Figure 7-3 shows a basic concept drawing of the interaction between supply pins VM and VDD, the output stage drivers and SDO supply line.
When 3 V ≤ VM ≤ VDD - VMDIFF, DRV81008-Q1 operates in Cranking Operative Range (COR). In this condition, the current consumption from VDD pin increases while it decreases from VM pin. Total current consumption remains within the specified limits.
Figure 7-4 shows the voltage levels at VM pin where the device goes in and out of COR. During the transition to and from COR, IVM and IVDD change between values defined for normal operation and for COR operation. The sum of both current remains within limits specified in Section 6.5.
When VM_UVLO ≤ VM ≤ VM_OP, it may be not possible to switch ON a channel that was previously OFF. All channels that are already ON keep their state unless they are switched OFF via SPI or via IN pins. An overview of channel behavior according to different VM and VDD supply voltages is shown in Table 7-2, Table 7-3 and Table 7-4 (the tables are valid after a successful power-up).
VDD ≤ VDD_UVLO | VDD > VDD_UVLO | |
VM ≤ 3 V | Channels cannot be controlled | Channels can be switched ON and OFF (SPI control)(RDS(ON) deviations possible) |
3 V < VM ≤ VM_OP | Channels cannot be controlled by SPI | Channels can be switched ON and OFF (SPI control)(RDS(ON) deviations possible) |
VM > VM_OP | Channels cannot be controlled by SPI | Channels can be switched ON and OFF |
VDD ≤ VDD_UVLO | VDD > VDD_UVLO | |
VM ≤ 3 V | Not available | Available (RDS(ON) deviations possible) |
3 V < VM ≤ VM_OP | Available (RDS(ON) deviations possible) | Available (RDS(ON) deviations possible) |
VM > VM_OP | Available | Available |
VDD ≤ VDD_UVLO | VDD > VDD_UVLO | |
SPI Registers | Reset | Available |
SPI Communication | Not available (fSCLK = 0 MHz) | Possible (fSCLK = 5 MHz) |