ZHCSQH2 July   2024 DRV81008-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active mode
          5. 7.3.2.1.5 Limp Home mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Switching Channels in parallel
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Input 0 Mapping Register
          4. 7.3.5.4.4  Input 1 Mapping Register
          5. 7.3.5.4.5  Input Status Monitor Register
          6. 7.3.5.4.6  Open Load Current Control Register
          7. 7.3.5.4.7  Output Status Monitor Register
          8. 7.3.5.4.8  Configuration Register
          9. 7.3.5.4.9  Output Clear Latch Register
          10. 7.3.5.4.10 Configuration Register 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Suggested External Components
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
      2. 8.2.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.1 Absolute Maximum Ratings

Over TJ = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise noted)
MINMAXUNIT

VM

Analog supply voltage

-0.3

42

V

VDD

Digital supply voltage

-0.3

5.75

V

VM_LD

Supply voltage for load dump protection

42

V

VM_SC

Supply voltage for short circuit protection

0

35

V

-VM_REV

Reverse polarity voltage, TJ(0) = 25 °C, t ≤ 2 min, RL = 70 Ω on all channels

-

18

V

IVM

Current through VM pin, t ≤ 2 min

-10

10

mA

|IL|

Load current, single channel

-

IL_OCP0

A

VDS

Voltage at power FET

-0.3

42

V

EASMaximum energy dissipation single pulse, TJ(0) = 25 °C, IL(0) = 2*IL_EAR

-

50

mJ

EASMaximum energy dissipation single pulse, TJ(0) = 150 °C, IL(0) = 400 mA

-

25

mJ

EARMaximum energy dissipation for repetitive pulses -IL_EAR, 2*106 cycles, TJ(0) = 85 °C, IL(0) = IL_EAR

-

10

mJ

VI

Voltage at IN0, IN1, nSCS, SCLK, SDI pins

-0.3

5.75

V

VnSLEEP

Voltage at nSLEEP pin

-0.3

42

V

VSDOVoltage at SDO pin-0.3VDD + 0.3

V

TA

Ambient Temperature

-40

125

°C

TJ

Junction Temperature

-40

150

°C

TstgStorage temperature

-55

150

°C

  • The short circuit protection feature does not support short inductance < 1 μH above 28 V.

  • Load dump is for a duration of ton = 400 ms; ton/toff = 10%; limited to 100 pulses.

  • For reverse polarity, TJ(0) = 25 °C, t ≤ 2 min, RL = 70 Ω on all channels. Device is mounted on a FR4 2s2p board according to JEDEC JESD51-2,-5,-7 at natural convection; the Product (Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 μm Cu, 2 * 35 μm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

  • For maximum energy dissipation, pulse shape represents inductive switch off: IL(t) = IL(0) x (1 - t / tpulse); 0 < t < tpulse.

  • Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

  • Fault conditions are considered as “outside” normal operating range.
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