The device has two independent integrated PWM generators. Each PWM generator can be assigned to one or more channels, and can be programmed with a different duty cycle and frequency.

Both PWM generators refer to a base frequency f_INT generated by an internal oscillator. This base frequency can be adjusted using FPWM bits as described below.

For each PWM generator, four parameters can be set:

• Duty cycle (bits DC0 for PWM Generator 0)

  • 8 bits are available to achieve 0.39% duty cycle resolution

  • When the micro-controller programs a new duty cycle, the PWM generator waits until the previous cycleis completed before using the new duty cycle (this happens also when the duty cycle is either 0% or100% - the new duty cycle is taken with the next PWM cycle)

  • The maximum duty cycle achievable is 99.61% (DC0 set to 11111111b). It is possible toachieve 100% by setting FREQ0 to 11b.

• Frequency (bits FREQ0, FREQ1, FCTR0 and FCTR1 select the divider for f_INT to achieve the needed duty cycle)

• Channel output control and mapping registers PWM_OUT and MAP_PWM

  • Any channel can be mapped to each PWM Generator

  • Together with 2 parallel input it is possible to have 4 independent PWM groups of channels with loweffort from the point of view of micro-controller resources and SPI data traffic.

Figure 7-11 expands the concept shown in adding the PWM Generators.

Figure 7-11 PWM Generator Mapping